SRAM Write Controller Reduces Bit Line Precharge Power
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Solution Overview
Problem
Static Random Access Memory (SRAM) consumes a significant portion of system-level dynamic power, often up to 90%, due to repeated precharging of bit lines during write cycles, which is inefficient and increases power consumption.
Innovation Solution
The SRAM design includes a write controller that selectively precharges bit lines only once for consecutive writes to the same word line, reducing the number of precharge cycles and thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are precharged for every write cycle, then write reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies local quality by selectively precharging only the specific bit lines that require it for each write operation, rather than precharging all bit lines uniformly. The write controller identifies the target bit lines based on the write address and applies precharge only to those specific lines, thereby maintaining write reliability for the targeted cells while reducing unnecessary power consumption from precharging unused bit lines.
2Reliability
If precharge is performed for every write operation, then write operation reliability is improved, but write cycle power consumption increases
Solution Approach 1:
The patent changes the parameter of precharge frequency from a fixed value (precharge every write cycle) to a variable value (precharge only when needed). The write controller dynamically adjusts the precharge operation based on the write address and the state of the storage cells, performing precharge only for bit lines that require it. This parameter change reduces the overall number of precharge operations, thereby reducing energy loss while maintaining write operation reliability when precharge is actually needed.
3Productivity
If consecutive writes to the same word line are performed, then productivity is improved, but power consumption increases due to repeated precharges
Solution Approach 1:
The patent applies preliminary action by performing a single precharge operation before a sequence of consecutive writes to the same word line. The write controller identifies when multiple writes are targeting the same word line and performs the precharge once at the beginning of the sequence, rather than repeating the precharge before each individual write. This preliminary precharge action maintains productivity by enabling rapid consecutive writes while significantly reducing power consumption by eliminating redundant precharge operations.
Data Source
AI summary
A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.