SRAM Write Driver Early Activation for Read-Before-Write Errors
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Solution Overview
Problem
Static random-access memory (SRAM) circuits face challenges with the 'wrong way read before write' problem, where late arrival of the write column select signal can cause incorrect data to be written due to bit line voltage drops during read operations.
Innovation Solution
The SRAM circuit incorporates a combinatorial logic circuit, such as a NAND gate, to provide a precharge signal based on the write column select signal and bit line precharge signal, allowing the write driver to start driving data onto the bit lines before they are fully charged, thus mitigating the read before write issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write column select signal arrives late during a read operation, then the bit line voltage drops causing incorrect data to be written, but waiting for the read operation to complete fully delays the write operation
Solution Approach 1:
The patent applies preliminary action by detecting the write column select signal arrival early and preemptively adjusting the bit line precharge timing before the read operation fully completes. The write driver is enabled to start driving data onto the bit lines before they are fully charged, based on early detection of the write column select signal, thus preventing the wrong way read before write issue while maintaining timing efficiency
Solution Approach 2:
The patent implements feedback by monitoring the write column select signal timing and using this information to dynamically control the precharge circuit and write driver enablement. The system detects when the write column select signal arrives and adjusts the bit line precharge timing accordingly, creating a closed-loop control mechanism that prevents incorrect writes while optimizing write operation timing
2Reliability
If the bit line precharge is completed fully before write operation, then correct data can be written, but this increases the timing margin requirements and reduces operational speed
Solution Approach 1:
The patent applies preliminary action by detecting the write column select signal arrival early and preemptively adjusting the bit line precharge timing before the read operation fully completes. The write driver is enabled to start driving data onto the bit lines before they are fully charged, based on early detection of the write column select signal, thus preventing the wrong way read before write issue while maintaining timing efficiency
Solution Approach 2:
The patent implements dynamics by making the bit line precharge timing adaptive rather than fixed. The precharge circuit is controlled to adjust its timing based on the actual arrival time of the write column select signal, allowing the system to dynamically optimize the balance between data correctness and operational speed for each operation cycle
Data Source
AI summary
A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.