SRAM Write Driver Circuit Partial Precharge Optimization

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Solution Overview

Problem

In static random access memory (SRAM) devices, the write operation is limited by the need to fully precharge bitlines, which consumes a significant portion of the cycle time and can lead to read failures and increased circuit complexity.

Innovation Solution

A write driver circuit that drives true and complement bitlines to a power supply and ground, allowing one to be grounded and the other to reach a high level simultaneously before precharging, and prevents full precharging of bitlines, thereby optimizing the precharge phase and reducing circuit complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bitlines are fully precharged to avoid read failures, then reliability is improved, but cycle time increases and productivity decreases

Engineering Contradiction:

Improveread failure avoidanceVSAvoidcycle time

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial precharging by precharging bitlines to a voltage level below the full rail voltage (e.g., below VDD) during the precharge phase. This partial precharge is sufficient to prevent read failures while avoiding the full precharge time penalty, thereby reducing the cycle time and improving productivity without sacrificing reliability.

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If bitlines are fully precharged, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveread failure avoidanceVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses partial precharging to a level below full rail, which simplifies the precharge circuit design and control logic compared to full precharge schemes. This reduces device complexity while still maintaining sufficient voltage levels to prevent read failures, thus improving reliability without increasing complexity.

Inventive Principle:

Principle #16Partial or excessive action

3Volume of stationary object

If write operations are performed with long bit lines, then memory capacity is improved, but write speed decreases and productivity is limited

Engineering Contradiction:

Improvememory capacityVSAvoidwrite speed

Core Design Contradiction:

Volume of stationary objectVSProductivity

Solution Approach 1:

The patent performs preliminary partial precharging of bitlines before the write operation begins. This preliminary action prepares the bitlines to an appropriate voltage level in advance, enabling faster write operations on long bit lines without compromising the memory capacity. The precharged state reduces the time required for subsequent write operations, thereby improving productivity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10510385B2Write scheme for a static random access memory (SRAM)

Publication Date: 2019.12.17 MARVELL ASIA PTE LTD

AI summary

A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.