SRAM Write Driver Single Shunt Topology Overdrive
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Solution Overview
Problem
Conventional SRAM write drivers face challenges in maintaining effective drive strength at reduced supply voltage levels, leading to weakened write noise margin and limitations in speed and power efficiency as technology advances.
Innovation Solution
A subsystem employing a single circuit element to overdrive the memory cell, utilizing a single shunt topology that replaces the conventional dual shunt arrangement, with a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell, enhancing drive strength and reducing driver area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If two NFETs are connected in series to overdrive the upper PFET in the SRAM cell, then the drive strength is increased, but the area of the driver circuit increases excessively
Solution Approach 1:
The patent segments the driver circuit into two separate drivers: a first driver that drives the first bit line and a second driver that drives the second bit line. Each driver contains only one NFET connected to ground, eliminating the need for series-connected NFETs. This segmentation allows each driver to achieve sufficient drive strength independently while minimizing the total driver area.
2Strength
If two NFETs are connected in series to overdrive the upper PFET, then the drive strength is increased, but the minimum supply voltage level is restricted
Solution Approach 1:
By dividing the driver function into two separate drivers, each handling one bit line, the patent eliminates the series NFET configuration. This allows each driver to operate with a single NFET connected directly to ground, providing stronger drive capability that can overcome the upper PFET even at reduced supply voltage levels, thus lowering the minimum supply voltage requirement.
3Strength
If the area of the driving NFET is increased to achieve sufficient drive strength, then the drive strength is improved, but the die area increases excessively
Solution Approach 1:
The patent divides the driving function into two separate drivers, each with one NFET. This segmentation allows the use of smaller NFETs compared to a single large NFET or series-connected NFETs, reducing the total die area while maintaining sufficient drive strength through the combined action of both drivers on their respective bit lines.
Solution Approach 2:
The patent merges the column selection function into the gate control of the NFETs in both drivers. The gate of each NFET receives both the write data signal and the column select signal, combining these functions into a single control mechanism. This integration eliminates the need for separate column selection circuitry, reducing overall driver area while maintaining drive strength.
4Area of stationary object
If a single NFET is used to overdrive the memory cell, then the driver area is reduced, but the drive strength is weakened
Solution Approach 1:
The patent segments the driving function into two separate drivers, each with one NFET. While each individual NFET is smaller than what would be needed in a conventional single-driver design, the combined drive strength of both NFETs operating on their respective bit lines provides sufficient overdrive capability to flip the SRAM cell state, thus maintaining drive strength while minimizing total driver area.
Data Source
AI summary
A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.