SRAM Write Enhancement Circuit for Low Voltage Stability
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Solution Overview
Problem
Semiconductor memory devices, particularly SRAM, face instability and reduced write performance when operating at low power supply voltages, which is exacerbated by increased bit line resistance in fine processes, leading to incorrect data storage and sensitivity to process variations.
Innovation Solution
The semiconductor memory device incorporates a cross-coupled inverter structure with a write enhancement circuit that reduces the gate-source voltage of pull-up transistors, utilizing stacked transistors and additional signal lines to enhance write performance and stability, including a write enhancement circuit that adjusts voltages to improve data flipping speed and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the power supply voltage is lowered to achieve low power operation, then power consumption is reduced, but SRAM stability deteriorates
Solution Approach 1:
The patent changes the voltage parameter dynamically by providing different gate-source voltages to the pull-up transistor during read and write operations. During read operations, a higher gate-source voltage maintains stability, while during write operations, a lower gate-source voltage enables proper data writing, thus resolving the contradiction between stability and write performance at low power supply voltages
Solution Approach 2:
The patent makes the transistor characteristics dynamic by controlling the gate-source voltage of the pull-up transistor to vary based on the operation mode (read or write). This dynamic adjustment allows the SRAM to adapt its behavior to different operational requirements, maintaining stability during reads while enabling writes at low voltages
2Productivity
If the gate-source voltage of the pull-up transistor is reduced to improve write performance, then data flipping capability is enhanced, but read stability deteriorates
Solution Approach 1:
The patent implements dynamic control of the pull-up transistor's gate-source voltage based on the operation mode. During write operations, the gate-source voltage is reduced to enhance data flipping capability, while during read operations, the gate-source voltage is increased to maintain read stability, thus resolving the contradiction between write performance and read stability
3Use of energy by stationary object
If conventional SRAM structures are used at low power supply voltages, then power consumption is reduced, but write ability deteriorates due to insufficient voltage headroom
Solution Approach 1:
The patent changes the gate-source voltage parameter of the pull-up transistor to be operation-mode dependent. By providing a lower gate-source voltage during write operations, the patent enables sufficient voltage headroom for data writing even when the overall power supply voltage is low, thus improving write ability while maintaining low power consumption
Data Source
AI summary
A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.