SRAM Write Operation Scheme Using Intermediary nMOSFETs
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Solution Overview
Problem
SRAM circuits face errors during write operations at the Slow-Fast process point due to stronger pull-up pMOSFETs and increased RC interconnect load, which worsens with longer interconnect lengths and higher loading, leading to incomplete bitline pulling to logical LOW voltage.
Innovation Solution
The implementation of a circuit configuration that reduces the RC load on write drivers by using pass nMOSFETs and NOR gates to assist in pulling bitlines to logical LOW voltage, thereby improving write operation margin at the SF process point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the SRAM uses low supply voltage, then power consumption is reduced, but the driver cannot pull the bitline fully to logical LOW voltage during write operations
Solution Approach 1:
The patent introduces an intermediary nMOSFET transistor connected between the bitline and ground. This intermediary device acts as an auxiliary pull-down transistor that activates during write operations to ensure the bitline reaches logical LOW voltage, while remaining inactive during normal operation to maintain low power consumption. The intermediary transistor resolves the contradiction by providing write assistance only when needed.
2Quantity of substance
If the interconnect length is increased, then the SRAM can accommodate more memory cells, but the RC load on write drivers increases causing incomplete bitline pulling to logical LOW
Solution Approach 1:
The patent deploys intermediary nMOSFET transistors at strategic locations within the memory array to compensate for increased RC load. These intermediary devices act as distributed boost elements that actively pull down bitlines in regions with longer interconnect lengths, ensuring uniform write operation margin across the entire memory array regardless of size.
Solution Approach 2:
The patent segments the memory array into multiple regions, each equipped with its own intermediary pull-down transistors. This segmentation allows localized compensation for RC effects in different parts of the array, enabling the SRAM to scale to larger capacities while maintaining reliable write operations throughout the entire structure.
3Adaptability or versatility
If the mux configuration is increased, then the SRAM can handle wider data words, but the write driver outputs are routed over longer distances resulting in larger RC interconnect load
Solution Approach 1:
The patent segments the wide data bus into multiple smaller bitline groups, each served by dedicated write drivers and intermediary transistors. This segmentation reduces the effective drive distance for each driver, maintaining strong drive capability even as the overall memory width increases, thereby preserving write operation reliability in wide-word SRAM configurations.
Data Source
AI summary
A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.