SRAM Write Margin Improvement via Selective Polysilicon Pre-Implantation
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Solution Overview
Problem
Conventional SRAM cell fabrication methods do not adequately enhance write margins, which is crucial for improving write performance in semiconductor memory.
Innovation Solution
A pre-implantation process is performed on the polysilicon layer before etching, where fifth-group elements are pre-implanted into NMOSFET regions and third-group elements into PMOSFET regions, excluding the SRAM PMOSFETs, using a pre-implantation photo mask to specifically avoid pre-implanting the Pull Up MOS regions, thereby increasing the equivalent resistance and reducing the doping concentration of the polysilicon gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-implantation process is applied to all polysilicon regions including SRAM PMOSFETs, then gate resistance is reduced and threshold voltage is adjusted, but equivalent resistance of Pull Up MOS decreases and write margins deteriorate
Solution Approach 1:
The patent applies different pre-implantation treatments to different regions: SRAM NMOSFETs receive pre-implantation to reduce resistance, while Pull Up MOS regions exclude pre-implantation to maintain high equivalent resistance. This local differentiation resolves the contradiction by optimizing each region's properties for its specific function.
Solution Approach 2:
The patent segments the polysilicon gate regions into distinct categories (SRAM NMOSFETs, Pull Up MOS, and other PMOSFETs) and applies selective pre-implantation processes to each segment. This segmentation allows independent optimization of resistance characteristics for different functional requirements.
2Reliability
If equivalent resistance of Pull Up MOS is reduced through pre-implantation, then threshold voltage is adjusted, but intermediate potential increases and write margins decrease
Solution Approach 1:
The patent applies pre-implantation selectively to non-SRAM PMOSFET regions while excluding Pull Up MOS regions, creating local quality differences that maintain high equivalent resistance in Pull Up MOS for improved write margins while still adjusting threshold voltage in other regions.
3Productivity
If pre-implantation is performed on SRAM NMOSFETs regions, then open current is enhanced, but manufacturing complexity increases due to selective masking requirements
Solution Approach 1:
The patent segments the polysilicon layer into SRAM NMOSFET regions, Pull Up MOS regions, and other PMOSFET regions, applying pre-implantation only to the first category. This segmentation enables selective enhancement of open current in SRAM NMOSFETs while managing manufacturing complexity through defined masking patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the write margins of SRAM cells by reducing the intermediate potential during write operations, enhancing the write performance and manufacturing capabilities, particularly in 45 nm technology.
Implementation Method 1
the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions
Data Source
AI summary
The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements.