SRAM Write Operation Using Precharge and Selective Bit Line Driving
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Solution Overview
Problem
SRAM performance is affected by power management techniques like DVFS and dual-rail configuration, leading to increased leakage current, timing variations, and reduced reliability, especially at lower voltages, making write operations less stable and more power-consuming.
Innovation Solution
A memory circuit with a differential writing scheme using a pair of bit lines, a precharge circuit, a multiplexer, and a pull-up circuit, where the bit lines are precharged to a first supply voltage, and the multiplexer and pull-up circuit selectively drive the zero bit to a low logic level and the non-zero bit to a high logic level, respectively, using logic gates and transistors to manage the write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS and dual-rail configuration are used for power management, then power consumption is reduced, but leakage current increases and timing variations occur
Solution Approach 1:
The precharge circuit precharges the bit lines to a first voltage level before the write operation begins, ensuring that the bit lines are in a known state and reducing timing variations during the write operation
Solution Approach 2:
The patent uses different voltage levels (first voltage and second voltage) for different phases of the write operation. The bit lines are precharged to a first voltage, then selectively driven to a second voltage level during the write operation, allowing optimization for both power consumption and reliability
2Use of energy by moving object
If lower voltages are used in dual-rail configuration, then power consumption is reduced, but write operation robustness and speed decrease
Solution Approach 1:
The precharge circuit prepares the bit lines in advance by charging them to the first voltage level, so that when the write operation begins, the bit lines are already in an optimal state for rapid switching, improving write speed without requiring higher operating voltages
Solution Approach 2:
The patent dynamically adjusts voltage levels during the write operation. The bit lines transition from a first voltage level during precharge to a second voltage level during the actual write operation, allowing the system to maintain high write speed and robustness only when needed while consuming less power during idle periods
3Use of energy by moving object
If lower voltages are used in dual-rail configuration, then power consumption is reduced, but write latency increases
Solution Approach 1:
The precharge circuit charges the bit lines to the first voltage level before the write operation begins, reducing the time required for voltage transitions during the write operation and thereby reducing write latency without increasing power consumption
Data Source
AI summary
A circuit including a memory cell, a pair of bit lines, a precharge circuit, a multiplexer, and a pull-up circuit is provided herein. The bit lines are coupled to the memory cell. The precharge circuit is coupled between the bit lines and configured to precharge each of the bit lines to approximately a first supply voltage to begin the write operation. The multiplexer is configured to select which bit line is a zero bit driven to a low logic level during the write operation and after the precharge circuit is turned off. After the write operation begins, the pull-up circuit is coupled to the bit lines and configured to select which bit line is a non-zero bit line driven to a high logic level.