SRAM Write Tracking Cells for Reliable Data Writing
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Solution Overview
Problem
Memory devices face reliability issues due to insufficient wordline and bitline pulses in writing data, particularly in the slow-NMOS fast-PMOS corner of process variations, leading to difficulties in writing '0' values into memory cells.
Innovation Solution
The implementation of write tracking techniques, where write tracking cells model the transition time of data storage elements, allowing the controller to adjust pulse lengths and intensities of wordline and bitline pulses to ensure accurate data writing, using a combination of hardware and software to manage these adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard wordline and bitline pulses are used for write operations, then the memory device operates with simple control logic, but the write reliability is insufficient particularly for writing '0' values in slow-NMOS fast-PMOS corner cases
Solution Approach 1:
The patent implements write tracking cells that model the transition time of data storage elements before actual write operations. These tracking cells perform preliminary characterization of the write pulse requirements, allowing the controller to pre-determine appropriate pulse lengths and intensities based on measured transition times rather than using fixed standard pulses.
Solution Approach 2:
The patent employs a feedback mechanism where the controller measures the transition time from write tracking cells and uses this measured information to adjust the pulse parameters for subsequent write operations. This closed-loop feedback ensures that pulse lengths and intensities are optimized based on actual device characteristics, improving write reliability while adapting to process variations.
2Reliability
If pulse lengths and intensities are increased to ensure reliable writing, then write reliability improves, but energy consumption and disturbance to non-accessed cells increases
Solution Approach 1:
The patent applies different pulse parameters locally to different memory cells based on their specific characteristics. By using write tracking cells that model individual cell transition times, the controller can tailor pulse lengths and intensities to each cell's requirements rather than applying uniform high-strength pulses to all cells, thereby reducing overall energy consumption while maintaining reliability.
Solution Approach 2:
The patent dynamically changes pulse parameters (length and intensity) based on measured transition times from write tracking cells. This allows the system to use minimal sufficient pulse strength for each write operation rather than consistently using high-strength pulses, optimizing the balance between write reliability and energy consumption.
3Reliability
If process variations are accommodated with fixed margins, then design robustness improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent transitions from static fixed-margin design to dynamic adaptation by implementing write tracking cells that measure actual transition times and enable the controller to adjust pulse parameters in real-time. This dynamic approach allows the system to accommodate process variations without requiring stringent manufacturing precision, as the control logic adapts to actual device characteristics rather than relying on conservative fixed margins.
Data Source
AI summary
Some aspects of the present disclosure relate to write tracking techniques for memory devices. In some embodiments, a memory device includes an array of SRAM cells, wherein each SRAM cell includes a pair of cross-coupled inverters having complimentary storage nodes, and a pair of access transistors that allow selective access to the complimentary storage nodes, respectively. To help ensure that wordline and bitline pulses are of sufficient length and intensity, one or more write tracking cells track a wordline tracking signal, which is representative of a wordline pulse applied to a wordline. In response to the wordline tracking signal, the write tracking cell internally generates a signal that models bitline loading, and provides an output tracking signal based on the wordline tracking and bitline loading signals. Bitline and/or wordline pulses can then be set based on the output tracking signal.