SRAM Write Tracking Circuit for Timing Control
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Solution Overview
Problem
Current SRAM technologies face challenges in efficiently executing write operations due to limitations in controlling the timing and voltage during write operations, which can lead to failed writes and increased power consumption.
Innovation Solution
A write tracking circuit is introduced that includes tracking memory cells arranged in a column, emulating the timing characteristics of the SRAM array, to control the duration of the write operation voltage reduction and pulse widths, ensuring accurate and efficient write operations by adapting to process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the operation voltage is lowered during write operation, then write margin reliability is improved, but the control precision of voltage duration and pulse timing deteriorates
Solution Approach 1:
The patent creates tracking memory cells that are identical copies of the actual SRAM memory cells, arranged in the same column configuration. These tracking cells replicate the exact timing characteristics and voltage responses of the real memory array during write operations. By using these copied structures, the system can precisely control and monitor the duration of lowered operation voltage and pulse timing without degradation, resolving the contradiction between improved write reliability through voltage lowering and maintained control precision.
Solution Approach 2:
The tracking circuit performs preliminary characterization of the write operation timing characteristics by using the tracking memory cells to pre-determine the optimal pulse width and voltage duration before actual write operations. This preliminary action allows the control circuit to precisely set the voltage lowering duration and pulse timing parameters, ensuring both improved write margin reliability and precise control without requiring real-time adjustments during the actual write operation.
2Reliability
If the pulse width on word lines is extended, then write operation completeness is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the word line pulse width and operation voltage duration based on real-time feedback from the tracking circuit. Instead of using a fixed extended pulse width that guarantees write completeness but increases power consumption, the system dynamically adjusts the pulse duration to the minimum required value determined by the tracking memory cells' characteristics. This dynamic adaptation ensures write operation completeness while minimizing unnecessary power consumption from extended pulsing.
Solution Approach 2:
The tracking circuit measures the actual timing characteristics of the memory array and uses this information to optimize the pulse width and voltage duration parameters. By changing these parameters based on measured performance rather than using conservative fixed values, the system achieves complete write operations with precisely controlled, minimized pulse widths that reduce power consumption while maintaining reliability.
3Reliability
If process, voltage, and temperature variations are compensated, then write operation robustness is improved, but circuit complexity increases
Solution Approach 1:
The tracking memory cells serve themselves by automatically tracking and characterizing the timing characteristics of the actual memory array under varying process, voltage, and temperature conditions. The tracking circuit requires no external calibration or complex compensation algorithms - it passively monitors the write operation timing through the replicated memory cell structure and provides direct feedback signals. This self-service approach achieves robust write operations across PVT variations without adding significant circuit complexity, as the tracking cells inherently adapt to environmental changes just like the real memory array.
Data Source
AI summary
An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.