SRAM Writing Circuit Using Dummy Replica for Negative Pulse Timing
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Solution Overview
Problem
Advanced semiconductor processes face challenges in fulfilling the conflicting requirements of data read and write operations in SRAM memory due to the difficulty in controlling the turn-on resistance of pass-gate transistors, especially at low operation voltages, leading to issues like read disturb and slow write cycles.
Innovation Solution
A writing system that uses a dummy replica bit-line to adaptively control the timing of introducing a negative pulse voltage on the bit-line, ensuring precise timing adjustments based on process, voltage, and temperature variations, thereby optimizing the turn-on resistance of pass-gate transistors for improved read and write accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the turn-on resistance of pass-gate transistors is reduced to improve write speed, then data write capability is improved, but read accuracy deteriorates due to read disturb
Solution Approach 1:
The patent applies periodic action by using a negative pulse voltage applied to the bit-line at specific timing during the write operation. This pulse is not continuous but periodic, applied only when needed to enhance pass-gate conduction during write while maintaining normal read operations without interference, thus resolving the contradiction between write speed and read accuracy
Solution Approach 2:
The patent changes the voltage parameter of the bit-line by applying a negative pulse voltage during write operations. This parameter change temporarily reduces the turn-on resistance of the pass-gate transistor during write, while the bit-line voltage returns to normal levels during read operations, preventing read disturb and maintaining read accuracy
2Reliability
If the turn-on resistance of pass-gate transistors is increased to improve read accuracy, then read disturb is reduced, but write speed deteriorates
Solution Approach 1:
The negative pulse voltage is applied periodically only during write operations at precise timing, enhancing conduction temporarily. During read operations, the bit-line operates at normal voltage levels, allowing the pass-gate transistor to maintain higher resistance for accurate reading without disturb
Solution Approach 2:
The negative pulse voltage is applied in advance at the beginning of the write operation to proactively reduce the turn-on resistance before the write process starts. This preliminary action ensures fast write speed from the outset without affecting subsequent read operations
3Speed
If a negative pulse voltage is applied to the bit-line to reduce turn-on resistance, then write capability is improved, but timing control complexity increases
Solution Approach 1:
The patent uses a dummy replica bit-line that mirrors the actual bit-line behavior to provide feedback for timing control. The negative pulse controller monitors the dummy replica bit-line and adjusts the pulse timing accordingly, creating a feedback mechanism that simplifies timing control while maintaining improved write capability
Solution Approach 2:
The patent creates a dummy replica bit-line that copies the electrical characteristics and behavior of the actual bit-line. This copy is used for timing control purposes, allowing the system to determine optimal pulse timing without directly interfering with the actual write operation, thus reducing timing control complexity
4Measurement precision
If process, voltage, and temperature variations are compensated for precise timing, then writing accuracy is improved, but control mechanism complexity increases
Solution Approach 1:
The dummy replica bit-line copies the electrical behavior of the actual bit-line under varying process, voltage, and temperature conditions. By monitoring this replica, the system can determine optimal pulse timing that compensates for PVT variations without requiring complex control mechanisms, thus improving writing accuracy while limiting complexity increase
Solution Approach 2:
The system uses its own dummy replica bit-line to automatically determine the optimal timing for negative pulse application. This self-service mechanism adapts to PVT variations inherently through the replica's behavior, improving writing accuracy without requiring external complex control mechanisms
Data Source
AI summary
SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.