SRAM Bit Cell XNOR Function for Computing-in-Memory
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Solution Overview
Problem
Deep neural networks (DNNs) face challenges in implementing high-precision MAC operations on resource-limited platforms due to memory bottlenecks in conventional CMOS ASIC accelerators, even with binary DNNs like XNOR-Net, as they require inefficient SRAM access for weights and intermediate data.
Innovation Solution
Customizing SRAM cells to perform XNOR and bit-counting operations, enabling computing-in-memory (CIM) by configuring SRAM cells with word lines, inverted word lines, bit lines, and complementary bit lines to generate voltage and current differences for binary output determination, thereby forming a binary neural network that supports efficient DNN and machine learning applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional CMOS ASIC accelerators are used with binary DNNs, then computation and storage costs are reduced, but memory access efficiency deteriorates due to row-by-row SRAM access requirements
Solution Approach 1:
The patent merges memory storage and computation functions by configuring SRAM bit cells to perform XNOR operations directly on stored weight values. The SRAM cell simultaneously stores the weight and performs the multiplication operation when activated by word lines, combining what were previously separate memory access and computation stages into a unified computing-in-memory operation.
Solution Approach 2:
The SRAM bit cell is designed to serve multiple functions: it acts as a storage element for weight values, a processing element for XNOR operations, and a contribution source for cumulative sum calculations. This multi-functionality eliminates the need for separate memory read and computation operations, directly addressing the memory access efficiency problem.
2Measurement precision
If high-precision MAC operations are implemented in DNNs, then computational accuracy is improved, but computational resource requirements increase
Solution Approach 1:
The patent changes the precision parameter of DNN operations from high-precision floating-point to binary precision (+1 or -1). This parameter change reduces the computational resource requirements while maintaining acceptable accuracy through the use of XNOR and bit-counting operations that are natively supported by the configured SRAM cells.
3Productivity
If parallel computation is exploited across PE arrays, then computational throughput is improved, but memory bottleneck persists due to inefficient SRAM access
Solution Approach 1:
The patent introduces a new dimension of parallelism by enabling simultaneous activation of multiple rows in the SRAM array through multiple word line pairs. Each activated row performs XNOR operations in parallel, and the complementary bit lines collect results from multiple rows simultaneously, creating a two-dimensional parallel computation structure that eliminates the memory bottleneck.
Data Source
AI summary
A static random access memory (SRAM) bit cell and a related SRAM array are provided. In one aspect, an SRAM cell is configured to perform an XNOR function on a first input value and a second input value. In another aspect, a number of the SRAM cells can be employed to form an SRAM array for supporting deep neural network and machine learning applications. The SRAM cell is coupled to a word line(s) and an inverted word line(s) that collectively define the first input value. The SRAM cell causes a voltage and/or current difference between a bit line(s) and a complementary bit line(s) coupled to the SRAM cell. By customizing the SRAM cell to enable the XNOR function and forming a binary neural network based on the SRAM array, it is possible to effectively implement computing-in-memory (CIM) for deep neural network and machine learning applications.