Sample Rate Converter Buffer Management for Wireless Audio

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Solution Overview

Problem

Conventional wireless audio devices face challenges in maintaining buffer stability due to asynchronous data transmission, leading to buffer overflow or underflow, which results in audible noise and artifacts, especially when clock frequencies drift and transmission failures occur.

Innovation Solution

Implementing a sample rate converter (SRC) that adjusts its data acquisition period and resampling ratio based on buffer filling levels, using digital filters to smooth data processing and control buffer levels, ensuring the buffer remains within target thresholds to prevent overflow and underflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed buffer size is used to handle asynchronous data transmission, then robustness against transmission failures is improved, but buffer overflow or underflow occurs due to clock frequency drift

Engineering Contradiction:
Improverobustness against transmission failuresVSAvoidbuffer level stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent implements dynamic buffer size adjustment by modifying the data acquisition period based on current buffer filling level and clock frequency drift estimates. The buffer transitions from a static fixed-size structure to a dynamic one that adapts its effective size through timing adjustments, preventing both overflow and underflow conditions while maintaining robustness against transmission failures.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors the buffer filling level and uses this feedback to adjust the data acquisition period. An estimator tracks clock frequency drift and provides feedback to the buffer manager, which then dynamically adjusts the acquisition timing. This closed-loop feedback mechanism ensures buffer level stability despite asynchronous transmission and clock drift.

Inventive Principle:
Principle #23Feedback

2Device complexity

If the data acquisition period is fixed, then simple timing control is achieved, but audible noise and artifacts occur due to buffer overflow or underflow

Engineering Contradiction:
Improvetiming control simplicityVSAvoidaudible noise and artifacts
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The data acquisition period transitions from a fixed value to a dynamically adjustable parameter. The system modifies the acquisition period based on real-time buffer filling level and estimated clock drift, enabling the timing control to adapt to varying conditions and prevent buffer overflow/underflow that cause audible artifacts.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the timing parameter (data acquisition period) dynamically based on system conditions. By adjusting this parameter in response to buffer filling level and clock drift estimates, the system prevents buffer overflow and underflow conditions that generate audible noise and artifacts.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If clock frequency drift is not compensated, then simple asynchronous reception is maintained, but buffer overflow or underflow occurs within less than 10 minutes of playback

Engineering Contradiction:
Improvereception processing simplicityVSAvoidcontinuous playback duration
Core Design Contradiction:
Device complexityVSDuration of action of stationary object

Solution Approach 1:

The system implements a feedback mechanism where an estimator continuously tracks clock frequency drift between transmitter and receiver. This drift estimate is fed back to the buffer manager, which adjusts the data acquisition period accordingly. This feedback loop compensates for frequency drift over time, enabling stable playback for extended durations without buffer overflow or underflow.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The buffer management system performs self-adjustment by automatically modifying the data acquisition period based on its own monitoring of buffer filling levels and clock drift estimates. This self-service mechanism enables the system to compensate for frequency drift and maintain stable operation without external intervention, extending continuous playback duration.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10534573B2Method for apparatus for sample rate conversion with unknown input and output clocks
Publication Date: 2020.01.14 SONOVA AG
  • US10534573B2 patent drawing
  • US10534573B2 patent drawing
  • US10534573B2 patent drawing

AI summary

Systems, methods and software for sample rate conversion with unknown input and output clocks are disclosed. In one embodiment, a method for an asynchronous transfer of audio data includes: receiving the audio data by an antenna of a receiver (RX); storing the audio data in an input buffer of the RX; and receiving data words from the input buffer by a sample rate converter (SRC). The consecutive data words are received from the input buffer at an adjustable period T. The method further includes tracking a filling level of the input buffer; and based on the filling level of the input buffer, adjusting the adjustable period T. When the filling level of the input buffer is below the target level of the input buffer, the adjustable period T is increased. When the filling level of the input buffer is above the target level of the input buffer, the adjustable period T is decreased.