SRC Internal Oscillator Design for Low-Cost Jitter-Tolerant Conversion
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Solution Overview
Problem
Conventional sample rate conversion (SRC) circuits require high precision operating clock signals, which increase their cost due to the need for external clock generators and precision PLLs, and are not cost-effective for digital signal processing systems.
Innovation Solution
Implementing an internal oscillator independent of external frequency control signals within the SRC circuit, allowing for the generation of an operating clock signal using low-quality clock generation circuits that can tolerate high jitter, thereby reducing the overall cost and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external high precision clock generators and precision PLLs are used to provide operating clock signals to SRC circuits, then clock signal precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the clock generation function from external high-precision components and implements it within the SRC circuit itself using a simple internal oscillator. This eliminates the need for external clock generators and precision PLLs, thereby reducing device complexity while maintaining acceptable clock signal precision for SRC operations.
Solution Approach 2:
The patent replaces expensive high-precision clock generation components with inexpensive low-precision oscillators. The invention demonstrates that high-precision clock signals are not necessary for SRC circuits to function adequately, allowing the use of cheap oscillators that generate clock signals with sufficient precision for the application.
2Measurement precision
If external clock generators are used to provide operating clock signals to SRC circuits, then clock signal quality is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive high-precision clock generation components with inexpensive low-precision oscillators. The invention demonstrates that high-precision clock signals are not necessary for SRC circuits to function adequately, allowing the use of cheap oscillators that generate clock signals with sufficient precision for the application.
Solution Approach 2:
The SRC circuit becomes self-sufficient by generating its own operating clock signal through an internal oscillator, eliminating the need for external clock generators. This self-service approach reduces manufacturing cost and simplifies the overall system architecture.
3Device complexity
If low-precision internal oscillators are used to generate operating clock signals, then device complexity and cost are reduced, but clock jitter increases
Solution Approach 1:
The patent converts the potential harm of clock jitter from low-precision oscillators into a benefit by demonstrating that SRC circuits are inherently tolerant of jitter. The conversion process involves showing that the SRC operation itself filters or tolerates jitter, transforming what would normally be a detrimental effect into an acceptable characteristic that enables the use of simple, low-cost oscillators.
4Ease of manufacture
If low-precision internal oscillators are used to generate operating clock signals, then manufacturing cost is reduced, but signal quality may degrade
Solution Approach 1:
The patent converts the potential harm of clock jitter from low-precision oscillators into a benefit by demonstrating that SRC circuits are inherently tolerant of jitter. The conversion process involves showing that the SRC operation itself filters or tolerates jitter, transforming what would normally be a detrimental effect into an acceptable characteristic that enables the use of simple, low-cost oscillators.
Data Source
AI summary
Because of the natural ability to reject clock jitter, the SRC circuits include an internal oscillator to provide an operating clock signal. The internal oscillator can be operated independently of any external frequency control signal, including input and output frame clocks. The internal oscillator can be implemented as a relatively low-cost fixed frequency oscillator. The use of a relatively low precision, inexpensive internal oscillator in an SRC circuit reduces the overall cost of SRC circuits while providing acceptable performance. Accordingly, reducing costs of SRC circuits also has a positive cost/benefit affect on the digital signal processing systems that use SRC circuits.