SRIO-to-PCIe Bridge Packet Routing with Deadlock Prevention
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Solution Overview
Problem
Existing packet routing and scheduling schemes for SRIO-to-PCIe bridges fail to meet both SRIO and PCIe ordering rules, leading to potential deadlocks and suboptimal throughput.
Innovation Solution
A configurable packet routing, buffering, and scheduling scheme that uses dynamic buffering and re-ordered packet dequeueing based on SRIO FTYPE and TTYPE, with per-flow backpressure and a circular-reorder queue to ensure both SRIO and PCIe ordering rules are met, preventing deadlocks and maintaining high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing packet routing and scheduling schemes are used in SRIO-to-PCIe bridges, then the system can operate with simple routing logic, but deadlock occurs and throughput decreases
Solution Approach 1:
The patent segments packets into different types (data packets, TLP packets, credit packets) and routes them through different paths and buffering mechanisms. Data packets use one set of buffers and scheduling logic, while TLP packets use another set, allowing independent optimization of each packet type's routing path to prevent deadlock while maintaining manageable complexity
Solution Approach 2:
The patent introduces intermediate buffering structures (ingress buffers, egress buffers, reordering buffers) that act as mediators between SRIO and PCIe protocols. These buffers decouple the two protocol domains, allowing packets to be temporarily stored and reorganized to satisfy both protocol ordering requirements without creating deadlock conditions
2Reliability
If packet routing follows strict ordering rules for both SRIO and PCIe, then ordering correctness is maintained, but throughput decreases due to blocking
Solution Approach 1:
The patent implements dynamic buffering and scheduling where buffer allocation and packet dequeueing orders are adjusted in real-time based on packet type, flow status, and buffer availability. The scheduling logic dynamically selects which packets to transmit next based on current system state, maintaining ordering requirements while maximizing throughput by avoiding unnecessary blocking
Solution Approach 2:
The patent changes key parameters including buffer watermarks, scheduling priorities, and packet routing decisions based on packet type (data vs. TLP) and flow conditions. By dynamically adjusting these parameters, the system maintains strict ordering compliance for each packet type while optimizing overall throughput through adaptive resource allocation
3Productivity
If dynamic buffering and re-ordered packet dequeueing are implemented, then throughput is optimized and ordering rules are met, but device complexity increases
Solution Approach 1:
The patent divides the buffering and scheduling function into separate, specialized modules: ingress buffer management, egress buffer management, reordering buffer management, and type-specific scheduling logic. Each module handles a specific aspect of packet flow, making the overall complex system manageable through functional segmentation and independent optimization of each component
Data Source
AI summary
A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.