SR-IOV Function Mapping Across Nested Virtual Machines

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Solution Overview

Problem

Nested virtual machines have limited access to single-root input-output virtualization (SR-IOV) capabilities, limiting scalability and functionality in virtual machine nesting scenarios.

Innovation Solution

Implement memory address mappings between host, guest, and nested virtual machines using an IOMMU to enable SR-IOV capabilities, allowing requests and responses to be passed through multiple levels of nested virtual machines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory address mappings are implemented using IOMMU to enable SR-IOV capabilities for nested virtual machines, then SR-IOV functionality and scalability are improved, but system complexity and configuration overhead increase

Engineering Contradiction:

ImproveSR-IOV capability accessVSAvoidmemory address mapping configuration

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mapping layer between host, guest, and nested virtual machine memory addresses. The IOMMU acts as a mediator that translates nested virtual machine I/O memory management unit addresses through guest virtual addresses to host physical addresses, enabling SR-IOV functionality without direct access complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements nested memory address spaces where guest virtual addresses are nested within host physical addresses, and nested virtual machine addresses are nested within guest addresses. This nested structure allows multiple levels of virtualization while maintaining a unified address translation path through the IOMMU.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Speed

If direct communication between virtual and physical functions is enabled across virtualization layers, then communication efficiency is improved, but security risks and access control complexity increase

Engineering Contradiction:

Improverequest-response communication speedVSAvoidaccess control security

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The IOMMU serves as a secure intermediary that mediates all communication between nested virtual functions and physical functions. It validates address translations and enforces access control policies, allowing fast direct communication while maintaining security through the intermediary translation layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms where the IOMMU monitors and validates address translation requests, providing feedback on access permissions. This ensures that communication speed is maintained while security constraints are enforced through continuous validation of the translation paths.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS12455760B2Passing single-root input-output virtualization functions to nested virtual machines

Publication Date: 2025.10.28 RED HAT LLC

AI summary

Single-root input-output virtualization (SR-IOV) can be enabled for nested virtual machines using mapping. In one example, a host hypervisor can assign at least two guest virtual functions to a guest virtual machine such that each guest virtual function maps to a respective host virtual function executed by a SR-IOV device. The first guest virtual function of the at least two guest virtual functions can be configured to act as a guest physical function. The host hypervisor can receive a request generated by a nested virtual function assigned to a nested virtual machine hosted by the guest virtual machine. In response to receiving the request, the host hypervisor can translate a guest memory address of the guest physical function to a host memory address for the guest physical function. The host hypervisor can forward the request to the guest physical function for fulfillment using the translated host memory address.