SRPG Flip-Flop Cell Layout for Low-Leakage State Retention
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Solution Overview
Problem
Current state retention power gated (SRPG) cells in integrated circuits face challenges in reducing leakage current and optimizing die area and power consumption, with non-clock state independent (CSI) SRPG cells being larger and more power-consuming than necessary, while clock state independent (CSI) SRPG cells have specific clock state requirements that limit their replacement.
Innovation Solution
The development of novel SRPG cells that include adaptable positive edge-clock-triggered and negative edge-clock-triggered non-CSI SRPG cells, which optimize die area and power consumption by enabling clock state-dependent operation, reducing the need for larger CSI SRPG cells and improving power gating functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If non-CSI SRPG cells are used to reduce die area and power consumption, then area and power are improved, but clock state requirements limit their applicability
Solution Approach 1:
The patent creates a universal SRPG cell design that can operate in multiple clock states (both positive edge and negative edge triggered) by using clock-select logic. This allows the same cell structure to replace both CSI and non-CSI SRPG cells regardless of clock state requirements, making the solution universally applicable to all flip-flop replacements while maintaining the area and power benefits of non-CSI cells.
2Adaptability or versatility
If CSI SRPG cells are used to meet various clock state requirements, then adaptability is improved, but die area and power consumption increase
Solution Approach 1:
The patent introduces dynamic clock-select logic that adapts the SRPG cell operation based on the actual clock state. The cell dynamically switches between positive edge-triggered and negative edge-triggered modes using control signals derived from the clock waveform, allowing a single static cell structure to provide dynamic adaptability to different clock states without requiring larger CSI cell dimensions.
3Loss of energy
If power gating is implemented to reduce leakage current, then leakage power is reduced, but state retention becomes challenging
Solution Approach 1:
The patent implements preliminary state capture by using transmission gates controlled by power gating signals to latch the data state before the power supply is completely cut off. The retention latch is pre-charged and prepared to hold the state, and the transmission gates are timed to close just as power gating begins, ensuring state retention is established before leakage becomes problematic during the powered-down mode.
Data Source
AI summary
A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.