Shared Receive Queue Polling with Dynamic CPU Core Groups

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Solution Overview

Problem

Existing storage node architectures face issues with asymmetric core processing loads leading to increased latency and limited scalability in RPC messaging due to core contention and resource sharing, especially in multi-core CPU environments.

Innovation Solution

Dynamically changing groups of CPU cores for polling shared receive queues (SRQs) based on system load thresholds, adjusting the number of core groups and cores per group to optimize latency and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If each RPC request/reply is associated with specific corresponding cores, then core processing specialization is improved, but latency increases when cores have asymmetric processing loads

Engineering Contradiction:
Improvecore processing specializationVSAvoidRPC processing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic core group configuration where the number of cores assigned to poll SRQs changes based on system load conditions. During low load, fewer cores poll SRQs to reduce contention; during high load, more cores are allocated to handle increased RPC traffic, optimizing both latency and throughput adaptively

Inventive Principle:
Principle #15Dynamics

2Productivity

If a shared queue is used to receive RPC requests/replies, then core utilization is improved, but resource contention among cores increases

Engineering Contradiction:
Improvecore utilizationVSAvoidcore contention
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system dynamically adjusts the number of polling cores based on system load thresholds. When load is low, fewer cores poll the shared queue to minimize contention; when load increases, more cores are allocated to polling, balancing resource utilization against contention overhead

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of polling core count based on system load conditions. By monitoring load metrics and adjusting the number of active poller cores, the system optimizes the balance between queue drainage efficiency and resource contention

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the number of cores available for RPC messaging increases, then throughput capacity is improved, but scalability is limited by heterogeneous core configurations

Engineering Contradiction:
ImproveRPC throughput capacityVSAvoidscalability across heterogeneous systems
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal core group abstraction that works across heterogeneous multi-core systems. By grouping cores and managing them as a unified resource pool rather than individual units, the solution achieves consistent behavior across different CPU configurations and enables scalable RPC messaging

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Loss of time

If poller cores are highly available for polling SRQs, then RPC processing latency is reduced, but system load handling capacity is limited

Engineering Contradiction:
ImproveRPC processing latencyVSAvoidsystem load handling capacity
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The system implements dynamic scaling of poller core availability based on system load. During low-load periods, a small number of dedicated poller cores maintain low latency for RPC processing. When system load increases, additional cores are allocated to polling duties, increasing throughput capacity while maintaining acceptable latency performance

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250370823A1Poller with shared receive queues and CPU groups for storage cluster
Publication Date: 2025.12.04 DELL PROD LP
  • US20250370823A1 patent drawing
  • US20250370823A1 patent drawing
  • US20250370823A1 patent drawing

AI summary

Techniques for dynamically changing groups of CPU cores for polling shared receive queues, providing a tradeoff between decreasing latency and increasing throughput of storage nodes using RPC messaging. The techniques include, upon initialization of a storage node, assigning all its CPU cores to the same core group. The techniques include, in response to detecting that its system load has been maintained above a threshold value for a specified time interval, increasing the number of core groups by a predetermined factor, and decreasing the number of cores assigned to each core group by the predetermined factor. The techniques include, in response to detecting that the system load has been maintained at a level less than the threshold value for the specified time interval, decreasing the total number of core groups by the predetermined factor, and increasing the total number of cores assigned to each core group by the predetermined factor.