SRR Command Generation Circuit for Bank-Active Read Timing
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Solution Overview
Problem
The JEDEC SPEC requirements for Status Register Read (SRR) in semiconductor memory devices are not satisfied when a bank active command is inputted before the read command, leading to abnormal termination of SRR operations.
Innovation Solution
A command generation circuit that enables the SRR command only when the device is in an idle state after an MRS command, and disables it after a read operation is ended, ensuring the SRR is automatically completed even if a read command is inputted after a bank active command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bank active command is inputted before the read command for SRR, then the device can perform bank activation operations, but the SRR operation is abnormally terminated and cannot be normally performed
Solution Approach 1:
The patent applies preliminary action by detecting the bank active command input timing before the SRR read command and proactively preventing the harmful effect. The command generation circuit detects when a bank active command is inputted and generates a signal to prevent the SRR operation from being terminated, ensuring the SRR can complete normally even when bank activation occurs first.
Solution Approach 2:
The patent uses an intermediary approach by introducing a command generation circuit that acts as a mediator between the bank active command and the SRR read command. This circuit generates a control signal that prevents the SRR operation from being terminated by the bank active command, allowing both operations to coexist without interference.
2Ease of manufacture
If the SRR is automatically ended according to JEDEC SPEC, then the specification requirements are met, but the SRR cannot be normally performed when read command is inputted after bank active command
Solution Approach 1:
The patent applies dynamics by making the SRR operation behavior adaptable rather than fixed. The command generation circuit dynamically adjusts the SRR operation completion behavior based on the timing of bank active commands. When a bank active command is detected before the SRR read command, the circuit prevents automatic termination, allowing the SRR to complete normally. This dynamic adjustment maintains specification compliance while enabling flexible operation modes.
3Ease of operation
If the read command for SRR is inputted in idle state after MRS, then the SRR can be started according to JEDEC SPEC, but the SRR operation is terminated when bank active command is inputted before the read command
Solution Approach 1:
The patent uses feedback by implementing a command generation circuit that continuously monitors the input timing of bank active commands and SRR read commands. When the circuit detects that a bank active command is inputted before the SRR read command, it generates a feedback signal to prevent the SRR operation from being terminated, ensuring reliable completion while maintaining the ease of operation specified in JEDEC SPEC.
Data Source
AI summary
There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.