SrTiO3 MIM Capacitor ALD Process for Low EOT
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Solution Overview
Problem
Current Metal-Insulator-Metal (MIM) capacitors for dynamic random access memory (DRAM) nodes face challenges in achieving Equivalent Oxide Thickness (EOT) of less than 0.5 nm and low leakage current densities, particularly due to incompatibility with standard logic semiconductor processing and high deposition temperatures, and require materials with high dielectric constants and low leakage currents.
Innovation Solution
A method for manufacturing MIM capacitors using a strontium-rich Sr x Ti y O z insulating layer with a Sr-to-Ti ratio greater than 1, deposited via Atomic Layer Deposition (ALD) at temperatures less than 300°C, utilizing a Sr(t-Bu3Cp)2 based precursor system, which reduces interfacial oxide thickness and leakage current, and is compatible with TiN bottom electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-K materials (ZrO2/Al2O3/ZrO2) are used in MIM capacitors, then the dielectric constant is insufficient (K<40), but using alternative materials like SrTiO3 requires high deposition temperatures (>350°C) and post-deposition anneals that are incompatible with TiN bottom electrodes
Solution Approach 1:
The patent changes the deposition temperature parameter from conventional high temperatures (>350°C) to low temperatures (≤300°C) by using modified ALD processes with specific precursors, enabling TiN electrode compatibility while maintaining high dielectric constant properties
Solution Approach 2:
The patent employs a composite dielectric structure with SrTiO3 as the high-K material combined with TiO2 interfacial layers, creating a multi-layer composite that achieves both high dielectric constant and low leakage current at compatible processing temperatures
2Manufacturing precision
If the Equivalent Oxide Thickness (EOT) is reduced to less than 0.5 nm, then the capacitor density improves, but the leakage current density increases beyond acceptable levels (>10^-7 A/cm²)
Solution Approach 1:
The patent introduces TiO2 interfacial layers as intermediary layers between the SrTiO3 dielectric and the TiN electrode, which passivate the interface and reduce leakage paths, enabling ultra-low EOT (<0.5 nm) while maintaining acceptable leakage current densities
Solution Approach 2:
The patent applies different material compositions and structures at different locations within the dielectric stack - specifically TiO2-rich interfacial regions near electrodes and SrTiO3-rich bulk regions, optimizing both EOT and leakage characteristics through spatially varying material properties
3Reliability
If noble metal electrodes (Ru, Pt) are used to achieve good dielectric characteristics with SrTiO3, then the capacitor performance improves, but compatibility with state-of-the-art logic semiconductor processing is lost
Solution Approach 1:
The patent replaces expensive noble metal electrodes (Ru, Pt) with TiN, which is a standard, cost-effective material in logic semiconductor processing, achieving comparable performance through optimized dielectric stack design rather than relying on noble metal properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in MIM capacitors with EOT of less than 0.5 nm and leakage current less than 5x10^-7 A/cm², while being compatible with standard logic semiconductor processing, and reduces the number of leakage paths by using Sr-rich grains with smaller diameters and a direct physical contact between the Ti-containing bottom electrode and the insulating layer.
Implementation Method 1
a low temperature Atomic Layer Deposition (ALD) process
Data Source
Figure 1~2
Figure 3a~3c
Figure 4~5
AI summary
A method is disclosed for manufacturing SrxTiyO3 based metal-insulator-metal (MIM) capacitors (10) using a low temperature Atomic Layer Deposition (ALD) process. Preferably TiN is used to form the bottom electrode (11). The Sr/Ti ratio in the SrxTiyO3 dielectric layer (12) of the capacitor can be varied to tune the electric properties of the capacitor. The dielectric constant and the leakage current of the SrxTiyO3 dielectric layer decrease monotonously with the Sr content of this SrxTi1-xO3 dielectric layer. By increasing the Sr content at the interface between the SrxTiyO3 dielectric layer and the TiN bottom electrode, the interfacial equivalent-oxide thickness (EOT) can be further reduced. The dielectric layer can also comprise Ba in addition to or instead of Sr, with the formulae BaSrTiO respectively BaTiO.