SS Block and Coreset Multiplexing for mmW Network Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In wireless communication systems, particularly in millimeter wave (mmW) systems, user equipment (UE) faces challenges in identifying the location of control resource sets (coresets) that contain additional system information necessary for communication with a base station, as these coreset resources are often mapped to a wide range of time and frequency resources, making it difficult for the UE to synchronize and access the network effectively.
Innovation Solution
The base station transmits an indication of the coreset configuration and the type of multiplexing used to multiplex the coreset with the synchronization signal (SS) block to the UE, allowing the UE to determine the location of the coreset and process the control information within it to identify the data channel containing additional system information, thereby facilitating communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the coreset resources are mapped to a wide range of time and frequency resources, then the control information can be transmitted more reliably, but it becomes difficult for the UE to identify the appropriate resources to monitor
Solution Approach 1:
The patent segments the coreset configuration information into two parts: Type0-PDCCH configuration (for initial access) and Type1-PDCCH configuration (for data transmission). This segmentation allows the UE to first identify the Type0 coreset using narrowband synchronization signals, then use that as a reference to locate the Type1 coreset, thereby solving the difficulty of identifying coreset resources while maintaining reliable control information transmission
Solution Approach 2:
The patent applies preliminary action by first transmitting the Type0-PDCCH configuration and associated synchronization signals to the UE before the actual data transmission. This preliminary configuration enables the UE to pre-identify and prepare for monitoring the Type1 coreset resources, reducing the complexity of real-time resource identification while ensuring reliable control channel operation
2Device complexity
If the SS block contains only basic synchronization signals, then the block structure remains simple, but additional system information cannot be transmitted effectively
Solution Approach 1:
The patent merges the SS block with associated PDCCH configurations (Type0 and Type1) and data channels into an integrated transmission structure. The SS block carries not only synchronization signals but also references to and configurations of the coreset resources, while the coreset configurations point to data channels carrying additional system information. This merging allows comprehensive information transmission without significantly increasing SS block structural complexity
Solution Approach 2:
The patent introduces coreset configuration information as an intermediary between the SS block and additional system information. The Type0-PDCCH configuration acts as a mediator that the UE can decode from the SS block, which then provides the configuration for Type1-PDCCH that carries the actual additional system information. This intermediary approach enables effective transmission of extensive system information while keeping the SS block itself relatively simple
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Methods, systems, and devices for synchronization signal (SS) block and control resource set (coreset) multiplexing are described. Generally, the described techniques allow a base station to indicate, to a user equipment (UE), the location of a coreset including control information that may be used by the UE. Specifically, a base station may transmit an indication of a coreset configuration and an indication of a type of multiplexing used to multiplex the coreset with an SS block in the SS block to a UE. Accordingly, the UE may receive the SS block, and the UE may determine the location of the coreset based on the coreset configuration and the indication of the type of multiplexing used to multiplex the coreset with the SS block. The UE may then process the control information included in the coreset to identify the location of a data channel including additional system information.