SSC Clock and Data Recovery Circuit for Static Phase Error Cancellation
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Solution Overview
Problem
In digital-based clock and data recovery (CDR) circuits with spread spectrum clocking (SSC), there is a residual static phase error between the input signal and the output clock signal due to differences in near-end and far-end SSC, which degrades receiver performance.
Innovation Solution
The CDR circuit incorporates a phase detector, digital loop filter, SSC demodulator, control code generator, and phase interpolator to adjust the phase of the clock signal, using SSC direction information to cancel the SSC component and reduce static phase error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spread spectrum clocking is used in the PLL to generate the reference clock signal, then clock signal distribution and jitter reduction are improved, but a residual static phase error occurs between the input signal and output clock signal due to differences in near-end and far-end SSC
Solution Approach 1:
The patent introduces an SSC demodulator as an intermediary component that processes the SSC-modulated clock signal. The demodulator extracts and removes the SSC modulation component, allowing the CDR circuit to operate with a clean reference clock signal that doesn't introduce static phase errors, thus resolving the contradiction between maintaining SSC benefits and eliminating phase error
Solution Approach 2:
The patent extracts the SSC modulation component from the reference clock signal using the SSC demodulator. By separating and removing the SSC component, the system maintains the clock distribution benefits of SSC while eliminating the harmful static phase error that would otherwise degrade receiver performance
2Device complexity
If the CDR circuit directly uses the SSC-modulated reference clock signal without demodulation, then the circuit complexity is reduced, but the static phase error degrades the phase alignment between input and output clock signals
Solution Approach 1:
The SSC demodulator serves as a necessary intermediary that, while adding a component to the circuit, enables accurate phase alignment by removing the SSC modulation. This intermediate step is crucial for achieving the desired phase alignment accuracy without requiring complex alternative approaches
Data Source
AI summary
The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR includes a phase detector, a digital loop filter, a first phase interpolator and a second phase interpolator. The PLL is configured to generate a first clock signal with SSC modulation and a control signal. The phase detector is configured to generate a detection result according an input signal and an output clock signal, wherein the input signal is with SSC modulation. The digital loop filter is configured to filter the detection result to generate a filtered signal. The first phase interpolator is configured to generate a second clock signal according to the filtered signal and the first clock signal. The second phase interpolator is configured to cancel an SSC component contributed by the first clock signal in the second clock signal to generate the output clock signal according to the control signal.