SSC CDR Circuit Using Demodulation to Cut Static Phase Error
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Solution Overview
Problem
In digital-based clock and data recovery (CDR) circuits with spread spectrum clocking, a residual static phase error occurs between the input signal and the output clock signal due to differences in near-end and far-end SSC, which degrades receiver performance.
Innovation Solution
A CDR circuit comprising a phase-locked loop (PLL), phase detector, digital loop filter, SSC demodulator, control code generator, and phase interpolator is used to generate a first clock signal with SSC modulation, compare phases, filter detection results, and adjust the phase of the clock signal to reduce static phase error by canceling SSC components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If near-end SSC is used in the reference clock signal and far-end SSC is used in the input signal, then spread spectrum clocking is implemented for both ends, but a residual static phase error occurs between the input signal and output clock signal
Solution Approach 1:
The patent extracts and removes the near-end SSC component from the reference clock signal using a demodulator before phase comparison. By separating and eliminating the unwanted SSC modulation, the system prevents the residual static phase error that would otherwise occur when comparing signals with different SSC characteristics.
Solution Approach 2:
The patent introduces an intermediate processing stage (demodulator and SSC cancellation circuit) between the reference clock generation and the phase detector. This intermediary removes the near-end SSC modulation, allowing clean phase comparison between the far-end SSC input signal and the reference clock without static phase error.
2Productivity
If phase comparison is performed between input signal with SSC modulation and output clock signal with SSC modulation, then clock and data recovery is achieved, but receiver performance is lowered due to residual static phase error
Solution Approach 1:
The patent extracts the harmful near-end SSC component from the reference clock signal before phase comparison. By removing this modulation, the system maintains clock and data recovery functionality while eliminating the residual static phase error that degrades receiver performance.
Solution Approach 2:
The patent converts the potentially harmful effect of SSC modulation differences into a benefit by using the demodulator to selectively remove only the near-end SSC component. This allows the system to maintain the benefits of SSC (jamming resistance, signal integrity) while eliminating the harmful static phase error, thereby improving receiver performance.
Data Source
AI summary
The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.