Separate SSC Chip for PLC Fiber Coupling Yield

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Solution Overview

Problem

The integration and miniaturization of planar lightwave circuits (PLCs) are hindered by large coupling losses when coupling high Δ waveguides with single mode fibers, as the mode fields mismatch, and existing spot-size converters (SSCs) complicate the manufacturing process, increasing costs and reducing yields.

Innovation Solution

A SSC chip with a straight waveguide and vertically or horizontally tapered waveguides is fabricated independently from the PLC chip, eliminating the need for end-waveguide SSCs and simplifying the PLC chip manufacturing process by forming spot-size converters with enlarged core dimensions, reducing the necessity for vertical and horizontal tapering in the PLC chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If spot-size converters are added to the end of light waveguides in the PLC chip to connect with fibers of different spot sizes, then coupling loss is reduced, but the manufacturing yield decreases due to additional SSC yield requirements

Engineering Contradiction:
Improvecoupling lossVSAvoidmanufacturing yield
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The invention divides the spot-size converter function from the PLC chip into a separate SSC chip. The SSC chip contains multiple spot-size converters that are independently fabricated and then bonded to the PLC chip, allowing each component to be optimized and manufactured separately, thus improving overall yield while maintaining low coupling loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The SSC chip acts as an intermediary component between the PLC chip and the fiber array. It provides the spot-size conversion function without being integrated into the PLC chip itself, thereby avoiding the yield penalty of combining multiple functions in a single chip while still achieving the desired optical coupling performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If vertically and horizontally tapered cores are created in the PLC chip to enlarge core diameter, then mode field matching is improved, but manufacturing cost increases due to additional processing steps

Engineering Contradiction:
Improvecoupling lossVSAvoidmanufacturing cost
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The invention separates the spot-size converter fabrication process from the PLC chip manufacturing process. The SSC chip is fabricated with tapered cores using specific processes, then bonded to the PLC chip. This segmentation allows the PLC chip to be manufactured with simpler, less costly processes while the SSC chip handles the complex tapering requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the approach to core dimension control by fabricating the SSC chip with pre-determined tapered core parameters (vertical and horizontal tapering) before bonding. This allows optimization of core dimensions for mode field matching without adding processing steps to the PLC chip manufacturing, thereby reducing overall manufacturing cost.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8538213B2SSC chip, fiber array attached with SSC, PLC module attached with SSC and method for manufacturing SSC
Publication Date: 2013.09.17 FURUKAWA ELECTRIC CO LTD
  • US8538213B2 patent drawing
  • US8538213B2 patent drawing
  • US8538213B2 patent drawing

AI summary

There is provided a SSC chip whose yield may be improved and whose processing steps may be simplified as compare to those of a prior art PLC chip having a light waveguide circuit to which a spot-size converter (SSC) is added, a fiber array attached with the SSC chip, a PLC module attached with the SSC chip and a method for manufacturing the SSC chip. The SSC chip has four spot-size converters and is fabricated separately from a PLC chip. Each SSC has a straight waveguide having the same core width and height with an end of an input/output waveguide of the PLC chip, a horizontally tapered waveguide in which the core width is enlarged in a tapered shape in the horizontal direction from the core width of the straight waveguide, a vertically tapered waveguide in which the core height is enlarged in a tapered shape in the vertical direction from the core height of the horizontally tapered waveguide and a spot-size enlarged portion whose core width and core height are both enlarged. Because it is unnecessary to fabricate the SSC at the end of the input/output waveguide of the PLC chip, a yield of the PLC chip may be improved.