SSC Clock Recovery Circuit for Large Frequency Shift Tracking
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Solution Overview
Problem
Existing clock recovery devices struggle to effectively recover a clock from degraded and stressed spread-spectrum clock (SSC) modulated data signals with large frequency shifts, leading to distorted waveforms and increased bit error rates.
Innovation Solution
A clock recovery circuit that includes a reference clock generation unit, a clock recovery unit, an FM demodulation unit, and a modulation signal generation unit, which together restore the original SSC modulated frequency from the FM demodulated signal, minimizing frequency deviation and improving clock recovery durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general-purpose clock recovery device is used to recover clock from SSC modulated data signal, then the device can handle small frequency deviations (±100 ppm), but it cannot handle large frequency shifts (5300 ppm) caused by SSC modulation
Solution Approach 1:
The invention uses a voltage-controlled oscillator (VCO) whose oscillation frequency can be dynamically adjusted by a control voltage. The VCO frequency is modulated according to the SSC modulation waveform, allowing the clock recovery device to track and follow the large frequency shifts (5300 ppm) caused by SSC modulation, thereby maintaining reliable clock recovery across varying frequency conditions
Solution Approach 2:
The invention changes the operating parameters of the clock recovery device by introducing SSC modulation to the VCO control voltage. This allows the device to adapt its frequency response dynamically, enabling it to handle both the nominal frequency and the large frequency deviations caused by SSC modulation, thus resolving the contradiction between reliability and frequency shift tolerance
2Object-affected harmful factors
If SSC modulation is applied to clock signal for EMC measures, then electromagnetic compatibility is improved, but frequency deviation increases making clock recovery difficult
Solution Approach 1:
The invention extracts the SSC modulation waveform from the received data signal and feeds it back to modulate the VCO frequency. This feedback mechanism allows the clock recovery device to compensate for the frequency deviations introduced by SSC modulation, maintaining stable clock recovery while preserving the EMC benefits of SSC modulation
Solution Approach 2:
The invention uses an intermediary SSC modulation waveform extraction and application mechanism. The extracted SSC waveform serves as a mediator between the received modulated signal and the VCO, enabling the system to track and follow frequency variations without being directly affected by the harmful electromagnetic interference that SSC modulation is designed to mitigate
3Measurement precision
If clock recovery is performed on degraded SSC modulated data signal, then bit error rate measurement can be conducted, but the recovered clock waveform becomes distorted with peak portions cut off
Solution Approach 1:
The invention performs preliminary SSC modulation on a reference clock signal using the extracted SSC waveform before using it for clock recovery. This preliminary action prepares the reference clock to match the frequency characteristics of the degraded received signal, enabling accurate clock recovery and BER measurement while preserving waveform integrity through the VCO's ability to track frequency variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables reliable clock recovery from SSC modulated data signals with large frequency shifts, reducing bit error rates and ensuring stable operation even with degraded signal conditions.
Implementation Method 1
a voltage-controlled oscillator that outputs an output signal of a frequency corresponding to an input control voltage... the voltage-controlled oscillator generates the reference clock by modulating a clock of the voltage-controlled oscillator
Implementation Method 2
a phase comparator that outputs a phase difference signal corresponding to a phase difference between a base clock having a predetermined frequency and the output signal of the voltage-controlled oscillator
Implementation Method 3
a charge pump that generates a charge/discharge current in response to the phase difference signal
Implementation Method 4
a loop filter that outputs a signal obtained by removing a high frequency component from the charge/discharge current
Implementation Method 5
a frequency modulation (FM) demodulation unit that performs FM demodulation on the SSC modulated clock recovered by the clock recovery unit
Data Source
AI summary
A clock recovery circuit includes a reference clock generation unit that generates a reference clock subjected to SSC modulation, a clock recovery unit that recovers an SSC modulated clock of a data signal subjected to the SSC modulation in synchronization with the reference clock, and a modulation signal generation unit that generates a modulation signal based on cycle information indicating a cycle of a FM demodulated signal obtained by performing FM demodulation on the SSC modulated clock recovered by the clock recovery unit and slope information indicating a slope of the FM demodulated signal, in which the reference clock generation unit generates the reference clock by performing the SSC modulation on a clock of a VCO with the modulation signal, and feeds back the reference clock subjected to the SSC modulation to the clock recovery unit.