SSC NOR Flash Cell Array ChiTel Programming Scaling
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Solution Overview
Problem
NOR flash memory cells face a technical roadblock in scaling down gate lengths below 100 nm due to the punch-through issue caused by high source-drain voltage potential differences during the Hot Carrier Injection programming scheme.
Innovation Solution
The implementation of the Channel Induced Ternary Electron (ChiTel) programming scheme, which applies no voltage bias to source electrodes and a low drain voltage, reducing programming current by a factor of 10 and eliminating the punch-through issue, allowing for gate lengths to be scaled down to minimum feature sizes below 100 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate length of NOR flash memory cells is scaled down to increase memory density, then memory density increases and storage cost per bit decreases, but the punch-through issue occurs due to high source-drain voltage potential differences during Hot Carrier Injection programming
Solution Approach 1:
The patent changes the programming parameters by applying no voltage bias to source electrodes and using low drain voltage (0V to 4V), which fundamentally alters the electrical conditions during programming. This parameter change eliminates the high source-drain voltage potential difference that causes punch-through, enabling gate lengths to be scaled down below 100nm while maintaining reliable programming operation
Solution Approach 2:
The patent substitutes the conventional Hot Carrier Injection (HCI) programming mechanism with a Channel Induced Ternary Electron (ChiTel) programming mechanism. This new mechanism uses low-energy electrons generated in the channel during read operations to program the cells, replacing the high-voltage HCI process and eliminating the punch-through issue that prevents further scaling
2Length of moving object
If the ChiTel programming scheme is implemented to eliminate punch-through and enable scaling, then gate lengths can be scaled down to minimum feature sizes below 100 nm, but programming current is reduced by a factor of 10
Solution Approach 1:
The ChiTel programming scheme utilizes electrons that are naturally generated in the channel during normal read operations to perform programming. Instead of requiring external high-current programming pulses, the system uses the read operation itself to generate the programming electrons, making the programming process self-service and dramatically reducing the programming current requirement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ChiTel programming scheme enables the scaling down of NOR flash memory cell gate lengths to minimum feature sizes below 100 nm, enhancing memory density and reducing storage costs per bit while maintaining fast access times and low operating voltages.
Implementation Method 1
the punch-through issue caused by the high source-drain voltage potential differences during the Hot Carrier Injection programming scheme
Data Source
AI summary
A Super Short Channel NOR-type (SSC NOR) flash array is disclosed. Upon the new Channel Induced Ternary Electron programming scheme for resolving the punch-through issue caused by the gate short channel of NVM cell devices, the gate length of NVM cell devices can be further shrunk below 100 nm for NOR flash array. The cell device of SSC NOR flash can be then scaled down to achieve the minimum cell sizes between 4F2 to 5F2, where F is the minimum feature size of a process technology node below 100 nm. In comparison with conventional NOR flash, the SSC NOR flash improves memory density resulting in cost reduction per bit storage. While on the benefit of increasing memory density and storage cost reduction, the invention preserves the typical NOR-type flash advantages over NAND flash on fast nanosecond-range access time, low operating voltages, and high reliability.