Adaptive Outer Coding for SSD Overprovisioning and Error Correction
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Solution Overview
Problem
Solid-state drives (SSDs) face a dilemma in maintaining user data storage capacity and overprovisioning levels over time due to increasing bit error rates and wear, where increasing the inner code rate to correct errors either reduces user data capacity or overprovisioning, and current technologies are economically undesirable for providing large initial overprovisioning levels.
Innovation Solution
A code adjustment circuit dynamically increases the inner code rate and decreases the outer code rate to maintain both user data capacity and overprovisioning levels above thresholds, ensuring efficient garbage collection and data transfer performance by adaptively managing code rates based on measured parameters like bit error rate and program/erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inner code rate is increased to correct read errors, then reliability is improved, but user data storage capacity deteriorates
Solution Approach 1:
The patent implements dynamic code rate adjustment where the inner code rate is increased adaptively based on measured bit error rates and program/erase cycle counts. The system transitions from static to dynamic code rate management, allowing the inner code rate to evolve with memory degradation while the outer code rate is adjusted compensatorily to maintain overall data capacity.
Solution Approach 2:
The system changes the parameter of code rate dynamically. Specifically, the inner code rate is increased in response to measured parameters (bit error rate, program/erase cycles) to compensate for memory degradation, while the outer code rate is decreased to maintain the overall code rate and data capacity. This parameter transformation resolves the contradiction by shifting the error correction burden from outer to inner codes.
2Reliability
If the inner code rate is increased to compensate for memory degradation, then reliability is improved, but overprovisioning level deteriorates
Solution Approach 1:
The patent transforms the parameter distribution between inner and outer codes. The inner code rate is increased to handle memory degradation, while the outer code rate is decreased proportionally. This parameter transformation ensures that the sum of inner and outer code rates remains constant, thereby maintaining the overall overprovisioning level while improving reliability through adaptive inner code strengthening.
Solution Approach 2:
The system recovers overprovisioning capacity by transitioning error correction functionality from outer codes to inner codes. As the inner code rate increases to compensate for degradation, the outer code rate is reduced, effectively recovering the overprovisioning level that would otherwise be consumed by increased outer code overhead.
3Reliability
If large initial overprovisioning levels are provided to accommodate future error correction needs, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces static overprovisioning with dynamic code rate adjustment. Instead of provisioning excessive capacity upfront, the system adaptively increases the inner code rate in response to measured memory degradation. This dynamic approach allows minimal initial overprovisioning to be sufficient, as the system evolves to meet future error correction needs without requiring large initial capacity reserves.
Solution Approach 2:
The system performs self-adjustment of code rates based on measured parameters from the memory itself. The code adjustment circuit monitors bit error rates and program/erase cycles, then autonomously adjusts the inner and outer code rates to maintain reliability. This self-service mechanism eliminates the need for conservative initial overprovisioning, allowing the system to optimize its own error correction capacity over time.
Data Source
AI summary
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.