SSD Bit Decoding with Selective Soft Reads for Lower Latency
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Solution Overview
Problem
Current SSD devices, especially those based on MLC and TLC technologies, face issues with increased bandwidth requirements and latency due to the need for multiple soft reference voltages, which exacerbates read access times and latency overhead as the number of bits per memory cell increases, leading to higher bit error rates and reduced reliability.
Innovation Solution
A method for decoding bits in SSD devices that uses fixed reference voltages to read first and second bits, with soft decoding based on additional soft information from these readings, and optional additional readings for reliability assessment, allowing for efficient soft decoding without increasing latency, particularly using LDPC codes for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple soft reference voltages are used for soft decoding, then decoding reliability is improved, but bandwidth requirements and latency increase
Solution Approach 1:
The patent extracts only the necessary soft information from memory cells for decoding, rather than performing multiple soft reads with multiple reference voltages. By selectively reading only the required soft bits and using them for LDPC decoding, the system achieves reliable error correction without the latency penalty of multiple reads.
Solution Approach 2:
The patent performs partial soft reading - reading only the minimum necessary soft information required for successful LDPC decoding, rather than performing excessive multiple soft reads with all possible reference voltages. This partial action approach achieves the needed decoding reliability while minimizing bandwidth consumption and latency.
2Reliability
If multiple soft reference voltages are used for soft decoding, then decoding reliability is improved, but bandwidth requirements increase
Solution Approach 1:
The patent extracts only the essential soft information from memory cells that is necessary for LDPC decoding success. By reading only the minimum required soft bits rather than performing multiple comprehensive soft reads, the system reduces bandwidth consumption while maintaining decoding reliability.
Solution Approach 2:
The patent implements partial soft reading by acquiring only the sufficient amount of soft information needed for successful decoding, avoiding the excessive bandwidth consumption that would result from multiple soft reads with all possible reference voltages.
3Quantity of substance
If the number of bits per memory cell increases, then storage capacity is improved, but bit error rates increase
Solution Approach 1:
The patent changes the decoding approach parameter from traditional hard decoding or excessive soft decoding to LDPC decoding with selective soft information. This parameter change enables the system to handle higher bit densities (MLC, TLC) successfully by using soft information more efficiently, thereby maintaining reliability despite increased storage capacity.
Data Source
AI summary
A method is proposed for decoding bits stored in memory cells of a solid state drive. Each memory cell comprises a floating gate transistor adapted to store a bit pattern, among a plurality of possible bit patterns, when programmed at a threshold voltage associated with that bit pattern, each threshold voltage being variable over the memory cells thereby defining, for each bit pattern, a corresponding threshold voltage distribution. The bit pattern of each memory cell comprises first and second bits, and the solid state drive is suitable for reading the bit patterns based on fixed reference voltages, each one designed to discern between two respective adjacent threshold voltage distributions, and on additional reference voltages different from the fixed reference voltages. The solid state drive is capable of soft decoding the read bit patterns based on soft information.