SSD Block Erase Scheduling for Lower Read Latency

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Solution Overview

Problem

Existing solid state drives (SSDs) experience significant read latency due to background erase operations in block erasable non-volatile memory, particularly in read-centric workloads, with erase latencies being several times greater than read latencies, leading to increased overall command latency.

Innovation Solution

Implementing piece-wise erase commands that are interleaved with read and write operations to manage erase operations without requiring intrusive suspend and resume commands, ensuring erase operations complete before a block is fully written, thus reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If background erase operations are implemented to improve data integrity, then data integrity is improved, but read latency increases significantly

Engineering Contradiction:
Improvedata integrityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The erase operation is divided into multiple smaller erase units (e.g., 4KB or 8KB segments) instead of erasing entire blocks at once. This segmentation allows the erase operation to be performed in parallel with read operations, reducing the impact on read latency while maintaining data integrity through complete erasure of all data blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by marking blocks as erased before actual erase operations complete. The controller maintains a mapping between logical and physical blocks, allowing read operations to proceed with marked blocks even before physical erasure finishes, thereby reducing read latency while ensuring data integrity through subsequent verification.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If erase operations are executed to complete before write operations, then data integrity is maintained, but read latency increases due to sequential execution

Engineering Contradiction:
Improvedata integrityVSAvoidcommand throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts the execution order and timing of erase and write operations based on real-time conditions. The controller can interrupt, suspend, or prioritize operations dynamically, allowing overlapping execution of erase and write operations on different blocks, thereby maintaining data integrity while improving command throughput and reducing read latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system introduces a new dimension of block management by implementing separate tracking mechanisms for erased blocks and available blocks. This allows the controller to manage erase operations in one dimension (ensuring completion for integrity) while simultaneously managing write operations in another dimension (optimizing throughput), resolving the contradiction between integrity and productivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If traditional block erase operations are used, then data integrity is ensured, but read latency increases due to long erase times

Engineering Contradiction:
Improvedata integrityVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The erase operation is divided into multiple smaller erase units (e.g., 4KB or 8KB segments) instead of erasing entire blocks at once. This segmentation allows the erase operation to be performed in parallel with read operations, reducing the impact on read latency while maintaining data integrity through complete erasure of all data blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system maintains continuous useful action by overlapping erase operations with read and write operations. Multiple operations proceed simultaneously on different blocks, ensuring that the erase process continues without idle time while other operations execute in parallel, thereby reducing overall latency while maintaining data integrity.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentEP4361828B1Method and apparatus for reducing read latency for a block erasable non-volatile memory
Publication Date: 2025.11.19 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • EP4361828B1 patent drawingFigure 1~2
  • EP4361828B1 patent drawingFigure 3
  • EP4361828B1 patent drawingFigure 4

AI summary

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.