SSD Memory Block Layout for RAIN Parity and Word Line Leakage
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Solution Overview
Problem
Existing RAIN error correction techniques in SSDs require a significant portion of memory space for over-provisioning and buffer storage, leading to reduced utilization of total memory space, and are ineffective in correcting data loss due to word line leakage.
Innovation Solution
A memory system is designed with super memory blocks and virtual memory blocks, where memory blocks from different planes form super memory blocks, and these are combined to create virtual memory blocks, allowing data to be stored and corrected efficiently with reduced over-provisioning and buffer usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAIN error correction techniques are implemented in SSDs, then data correction capability is improved, but memory space utilization deteriorates due to significant over-provisioning and buffer requirements
Solution Approach 1:
The patent segments the memory space into data regions and separate correction code regions, organizing memory blocks into groups where correction codes are stored in dedicated regions rather than mixing with data. This segmentation allows efficient use of correction codes while maintaining data integrity, resolving the contradiction between error correction capability and memory space utilization.
Solution Approach 2:
The patent introduces a new dimensional organization by creating cross-group correction relationships, where correction codes for one group of memory blocks are stored in different groups. This multi-dimensional organization optimizes the distribution of correction codes across the memory space, improving both correction effectiveness and space utilization.
2Reliability
If RAIN error correction techniques are implemented, then error correction functionality is improved, but device complexity increases due to buffer storage requirements
Solution Approach 1:
The patent extracts the correction code storage function from the main data storage operations and implements it through a separate mechanism using the host buffer. By taking out the buffer management task from the SSD controller and assigning it to the host system, the patent reduces the complexity of the SSD device while maintaining comprehensive error correction functionality.
Solution Approach 2:
The patent makes the host buffer serve multiple functions: it acts as both a data buffer for normal operations and as a correction code buffer for error correction. This multi-functionality eliminates the need for dedicated correction code buffers in the SSD, reducing device complexity while maintaining error correction capabilities.
Data Source
AI summary
Examples of the present disclosure disclose a memory system and an operation method thereof and a storage device and an operation method thereof. The memory system includes a memory device and a memory controller, the kth memory blocks in memory planes in the memory device form one super memory block, super memory blocks form one virtual memory block, the mth physical pages coupled with the nth word lines in the memory planes from a same super memory block in the virtual memory block form one virtual physical page, the virtual physical pages from super memory blocks in a same virtual memory block form one strip; and the memory controller is configured to: receive memory data that needs to be written to a strip; generate parity check data of the strip according to the memory data; and send the memory data and the parity check data to the memory device.