SSD Buffer Chip Layout for Low-Capacitance Channel Signaling
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Solution Overview
Problem
As the storage capacity of solid state drives (SSDs) increases, the number of nonvolatile memory chips connected to each channel grows, leading to increased load and decreased operating speed due to parasitic capacitance and signal reflection issues.
Innovation Solution
The SSD design includes a substrate with redistribution layers and buffer chips connected through flip chip bonding and wire bonding, dividing nonvolatile memory regions across channels to reduce parasitic capacitance and improve signal integrity, with some buffer chips using flip chip connections and others using wire bonding to manage signal transmission effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of nonvolatile memory chips connected to each channel increases to increase storage capacity, then storage capacity is improved, but operating speed decreases due to increased load and parasitic capacitance
Solution Approach 1:
The patent divides nonvolatile memory chips into multiple groups, with each group connected to a different channel. The controller is divided into multiple channel controllers, each managing a specific group of memory chips. This segmentation reduces the number of chips per channel, thereby reducing parasitic capacitance and maintaining operating speed while achieving high storage capacity through parallel channels.
2Quantity of substance
If the number of nonvolatile memory chips connected to each channel increases, then storage capacity is improved, but signal integrity deteriorates due to signal reflection issues
Solution Approach 1:
The patent segments memory chips across multiple channels to reduce signal reflection issues on each individual channel.
Solution Approach 2:
Buffer chips are introduced as intermediary components between the controller and nonvolatile memory chips. These buffers act as signal conditioning stages that reduce signal reflection and maintain signal integrity across the extended data paths required for high-capacity configurations.
3Reliability
If buffer chips are connected using wire bonding to reduce parasitic capacitance, then signal integrity is improved, but device complexity increases due to multiple connection methods
Solution Approach 1:
The patent applies different connection methods to different buffer chips based on their specific requirements. Some buffer chips use wire bonding for reduced parasitic capacitance in critical signal paths, while others use flip chip bonding for higher density connections. This localized application of connection techniques optimizes signal integrity where needed while managing overall device complexity.
Data Source
AI summary
A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.