SSD Write Buffer ECC Scheme for Early NAND Buffer Release
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Solution Overview
Problem
The write performance of solid-state drives (SSDs) is hindered by the insufficient size of the write buffer, leading to degraded performance due to insufficient storage capacity, which also increases power consumption and costs.
Innovation Solution
A memory system comprising a volatile write buffer, nonvolatile NAND flash memory, and a controller that employs multiplane programming and error correction codes (ECC) to optimize write operations, allowing for early release of buffer space and efficient data recovery, using Level 1 ECC for single-page errors and Level 3 ECC for errors across multiple pages or chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the buffer size is reduced to lower power consumption and costs, then power consumption and costs decrease, but write performance degrades due to insufficient storage capacity
Solution Approach 1:
The patent segments the buffer management into multiple independent planes (Plane 0, Plane 1, Plane 2, Plane 3), each capable of autonomous write operations. This allows the system to utilize smaller buffer spaces more efficiently by distributing data across multiple segments, thereby maintaining write performance while reducing overall buffer size and associated power consumption.
Solution Approach 2:
The patent implements preliminary error correction code generation at multiple levels (Level 1 ECC per page, Level 3 ECC per chip) before data is fully written to the buffer. This preliminary action ensures data integrity is established early, allowing the system to operate with smaller buffer spaces without compromising reliability, thus reducing power consumption while maintaining performance.
2Ease of manufacture
If the buffer size is reduced to lower costs, then costs decrease, but write performance degrades due to insufficient storage capacity
Solution Approach 1:
The patent divides the buffer into multiple planes that can operate independently with smaller individual buffer spaces. This segmentation allows the system to achieve the same write performance with a smaller total buffer capacity, reducing manufacturing costs while maintaining productivity through parallel plane operations.
Solution Approach 2:
The patent changes the operational parameters by implementing multiplane programming with independent plane control and multi-level ECC schemes. These parameter changes enable the system to optimize write performance within smaller buffer capacities, reducing the need for large expensive buffers while maintaining high write speeds.
3Productivity
If multiplane programming with early buffer release is implemented, then buffer turnover rate improves and write performance enhances, but system complexity increases
Solution Approach 1:
The patent segments the buffer into multiple planes with independent management, allowing early release of individual planes once their data is written to NAND flash. This segmentation enables sophisticated buffer turnover optimization without requiring a completely complex new system architecture, as each plane can be managed relatively independently.
Solution Approach 2:
The patent performs preliminary error correction encoding (Level 1 and Level 3 ECC) before buffer release, ensuring data integrity is established in advance. This preliminary action allows the system to safely release buffer spaces earlier without compromising data reliability, improving turnover rate while managing complexity through structured pre-processing.
4Reliability
If multi-level ECC is implemented for error correction, then data integrity is maintained, but processing complexity increases
Solution Approach 1:
The patent segments error correction into hierarchical levels: Level 1 ECC applied to individual pages and Level 3 ECC applied to groups of pages across multiple chips. This segmentation allows complex error correction to be broken down into manageable, independent stages, maintaining data integrity while controlling processing complexity through modular implementation.
Solution Approach 2:
The patent performs preliminary error correction encoding at multiple levels before data is written to the buffer and NAND flash. This preliminary action ensures that error correction is established in advance, allowing the system to maintain high data integrity while managing complexity through structured pre-processing rather than complex real-time correction.
Data Source
AI summary
According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.