SSD Controller Buffer and Sequencer for AES Encryption Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current solid-state drive (SSD) systems face latency issues during data encryption and decryption due to the sequential processing of data by AES cores, which limits communication speed and increases circuit size when trying to reduce latency by increasing the number of AES cores.
Innovation Solution
The SSD system employs a buffer to hold and sequentially output data to AES cores, allowing concurrent processing without waiting for previous data to be encrypted, and includes separate sequencers for receiving and transmitting data to reduce latency and maintain a manageable circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of AES cores is increased to reduce latency, then data encryption and decryption speed is improved, but circuit size increases
Solution Approach 1:
The buffer unit holds write data before encryption, allowing the system to prepare data in advance and output multiple units of data in sequence to the AES cores. This preliminary preparation enables continuous data flow to encryption cores without waiting for previous data to be processed, reducing latency without requiring additional cores
Solution Approach 2:
The sequencer continuously outputs multiple units of data from the buffer to the AES cores in sequence, ensuring that the encryption cores always have data to process. This continuous data supply eliminates idle time in the encryption pipeline, maintaining high utilization of the existing AES cores without increasing circuit size
2Speed
If the number of AES cores is increased to enhance communication speed, then data transfer rate is improved, but device complexity increases
Solution Approach 1:
The write data is divided into multiple units of data that are sequentially output from the buffer to the AES cores. This segmentation allows parallel processing of multiple data units through the same AES cores, achieving high communication speed without needing proportionally more encryption cores, thus avoiding increased device complexity
Solution Approach 2:
The sequencer acts as an intermediary between the buffer and AES cores, managing the sequential output of multiple data units to the encryption cores. This intermediary component coordinates data flow efficiently, enabling high-speed communication through structured data distribution without requiring a complex increase in AES core数量
Data Source
AI summary
A memory system includes a controller configured to write data to a nonvolatile memory. The controller includes a buffer unit configured to hold write data including a plurality of pieces of unit data, a sequencer configured to receive the write data from the buffer unit and individually output the plurality of pieces of unit data sequentially, and a plurality of cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer. The buffer is further configured to output the plurality of pieces of unit data sequentially to the sequencer, such that a last piece of unit data is output consecutively after a preceding piece of unit data is output.