Solid State Drive Buffer Chip Reduces Skew
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Solution Overview
Problem
The increased capacity of solid state drives due to overlapping semiconductor memory chips leads to reliability issues due to higher resistance components, resulting in communication channel speed toggles and increased skew.
Innovation Solution
A solid state drive design incorporating a nonvolatile memory, random access memory, and a memory controller with a buffer chip that directly exchanges data between the host interface, memory interface, and random access memory, reducing the load on the memory controller and improving communication efficiency by using separate input/output lines and control signals for each nonvolatile memory chip group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of semiconductor memory chips is increased to enhance storage capacity, then the storage capacity is improved, but the resistance components increase causing communication channel speed degradation and skew
Solution Approach 1:
A buffer chip is introduced as an intermediary component between the memory controller and multiple nonvolatile memory chips. The buffer chip receives commands from the memory controller and distributes them to appropriate memory chips, while also buffering data transfers. This intermediary structure reduces the direct communication load on the memory controller and mitigates the skew and resistance issues that arise from connecting numerous memory chips directly to the controller, thereby maintaining communication reliability while supporting increased storage capacity.
Solution Approach 2:
The system is segmented into distinct functional modules: a memory controller, a buffer chip, and multiple nonvolatile memory chips arranged in groups. The buffer chip acts as a intermediate layer that segments the direct communication path between the controller and memory chips. This segmentation allows the system to scale to more memory chips (increasing capacity) while the buffer chip manages the communication overhead, preventing the degradation of communication reliability that would occur with direct connections.
2Quantity of substance
If multiple nonvolatile memory chips are connected directly to the memory controller, then the storage capacity is increased, but the input/output pad loading on the memory controller increases causing performance degradation
Solution Approach 1:
The buffer chip serves as an intermediary that handles data buffering and command distribution between the memory controller and multiple nonvolatile memory chips. By introducing this intermediate layer, the memory controller does not need to directly manage all communication with numerous memory chips, reducing its I/O pad loading and maintaining communication efficiency while supporting expanded storage capacity.
Solution Approach 2:
The communication architecture is segmented into two levels: the memory controller communicates with the buffer chip at one level, and the buffer chip communicates with individual memory chip groups at another level. This segmentation distributes the I/O loading, preventing the memory controller from being overwhelmed by the sheer number of memory chips, thereby maintaining productivity while enabling capacity expansion.
Data Source
AI summary
A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.