SSD Control Module Caching Code and Data for Processor Access

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Solution Overview

Problem

Current data processing systems face inefficiencies due to the slower data access rates of disk drives compared to processors, leading to waiting times for code and data retrieval, especially in volatile system memories.

Innovation Solution

A control module for a solid-state disk (SSD) with a cache memory and dual interfaces is introduced, allowing for direct interfacing with a processor and caching of code and data from nonvolatile semiconductor memory, enabling faster access and reducing reliance on external memory loading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If disk drive is used for storing code and data, then nonvolatile storage is achieved, but data access rate is slower than processor execution rate

Engineering Contradiction:
Improvenonvolatile storageVSAvoiddata access rate
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The storage system is segmented into two distinct components: a nonvolatile storage device for persistent code and data storage, and a volatile cache memory for high-speed data access. This segmentation allows each component to optimize for its specific function, resolving the contradiction between nonvolatile storage and fast access speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A cache memory acts as an intermediary between the processor and the nonvolatile storage device. The cache memory stores frequently accessed code and data, serving the processor at high speed while the nonvolatile device provides persistent storage. This intermediary layer eliminates the direct performance bottleneck between the processor and nonvolatile storage.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If system memory is used for fast code and data access, then data access rate is improved, but data is lost when power is turned off

Engineering Contradiction:
Improvedata access rateVSAvoiddata persistence
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The memory system is segmented into volatile system memory for high-speed access during operation and nonvolatile storage for persistent data retention. This segmentation allows the system to achieve both fast access (from volatile memory) and data persistence (from nonvolatile storage) without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache memory serves as an intermediary that bridges volatile and nonvolatile storage. It provides the processor with fast access to frequently used data while automatically maintaining copies in nonvolatile storage, thus ensuring both speed and persistence without requiring direct processor awareness of the dual-storage architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If host adapter loads code and data from disk drive to system memory, then data is available for processing, but processor waits for loading completion

Engineering Contradiction:
Improvecode and data availabilityVSAvoidprocessor waiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The cache memory performs preliminary action by pre-loading frequently accessed code and data from nonvolatile storage into the fast volatile memory domain. This allows the processor to access data immediately without waiting for the host adapter to load it from the disk drive, significantly reducing processor waiting time and improving productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cache memory acts as an intermediary buffer between the slow disk drive and the fast processor. It absorbs the time discrepancy by pre-loading data, allowing the processor to operate at full speed while the host adapter continues loading data in the background, eliminating waiting time and improving overall productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8856423B1Dual-purpose nonvolatile memory for code and data storage
Publication Date: 2014.10.07 MARVELL ASIA PTE LTD
  • US8856423B1 patent drawing
  • US8856423B1 patent drawing
  • US8856423B1 patent drawing

AI summary

A control module for controlling a solid-state disk (SSD) includes a first interface, a cache memory, and a second interface. The first interface interfaces a nonvolatile semiconductor memory (NVM) of the SSD to a processor that is located externally to the SSD. The cache memory selectively caches at least one of code and data from the NVM. The second interface interfaces the cache memory to the processor and outputs portions of at least one of code and data from the cache memory to the processor.