SSD Cache ECC and Checksum Scheme for NAND Endurance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern 25-nm two-bit MLC NAND flash SSD caches have limited endurance due to high program/erase cycles in datacenter workloads, such as TPC-C, leading to a short service lifetime, which existing techniques like wear leveling, Retention Relaxation, and increased ECC strength do not adequately address.
Innovation Solution
A caching method that encodes data words into codewords with a checksum parity portion and error correction code parity portion, allowing for bit error correction and validation, and dynamically adjusts ECC parity bit length based on error rates to extend the cache memory's program/erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MLC NAND flash is used as cache memory to optimize storage performance, then small and random read performance is improved, but service lifetime is reduced due to limited endurance of approximately 3000 program/erase cycles
Solution Approach 1:
The patent changes the parameter of error correction capability by implementing a two-layer coding scheme with checksum and ECC, dynamically adjusting the strength of error correction based on observed error rates to extend the service lifetime of MLC NAND flash cache memory while maintaining read performance
Solution Approach 2:
The patent applies beforehand cushioning by pre-encoding data with checksum and ECC parity bits before writing to cache memory, creating a protective buffer against bit errors that accumulates over time and allows the system to withstand higher program/erase cycle counts
2Reliability
If ECC strength is increased with constant data-to-parity ratio to improve endurance, then program/erase cycle tolerance is improved, but storage capacity is reduced
Solution Approach 1:
The patent segments the error correction mechanism into two distinct layers: a checksum layer for detecting uncorrectable errors and an ECC layer for correcting bit errors. This segmentation allows each layer to be optimized independently, achieving high endurance without proportionally increasing the parity overhead and capacity loss
Solution Approach 2:
The checksum mechanism serves as an intermediary between the data and the ECC mechanism, filtering out completely corrupted codewords before they reach the ECC decoder. This intermediary layer reduces the burden on ECC, allowing weaker ECC configurations that preserve more storage capacity while still achieving high overall reliability
Data Source
AI summary
In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein.