SSD Cache Management via Preloading and Write Merging

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Solution Overview

Problem

Standard cache replacement policies in SSDs lead to cache pollution, especially with many small write requests, which negatively impacts SSD performance and endurance.

Innovation Solution

The SSD controller optimizes cache management by preloading data offline in read-only cache mode and minimizing write requests to the NAND flash memory by writing at a small granularity and evicting data in a way that reduces backend writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If standard cache replacement policies are used in SSD, then cache management is simple, but cache pollution occurs and performance deteriorates

Engineering Contradiction:
Improvecache management simplicityVSAvoidSSD performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies preliminary action by preloading data into the cache before it is actually needed. The SSD controller proactively loads data from NAND flash into the cache buffer in advance, so that when read requests arrive, the data is already available in the cache, avoiding cache pollution from reactive replacement policies and improving read performance.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If standard cache replacement policies are used in SSD, then cache management is simple, but cache hit rate decreases

Engineering Contradiction:
Improvecache management simplicityVSAvoidcache hit rate
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by preloading data into the cache before it is actually needed. The SSD controller proactively loads data from NAND flash into the cache buffer in advance, so that when read requests arrive, the data is already available in the cache, avoiding cache pollution from reactive replacement policies and improving read performance.

Inventive Principle:
Principle #10Preliminary action

3Speed

If write requests are processed immediately in SSD, then write speed is fast, but number of backend writes increases and endurance decreases

Engineering Contradiction:
Improvewrite speedVSAvoidSSD endurance
Core Design Contradiction:
SpeedVSDuration of action of stationary object

Solution Approach 1:

The patent applies merging by combining multiple small write requests into larger write operations. The SSD controller buffers incoming write requests and merges them into larger write units before writing to NAND flash, reducing the total number of backend writes while maintaining fast write performance, thereby extending SSD endurance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies preliminary action by preloading data into the cache before it is actually needed. The SSD controller proactively loads data from NAND flash into the cache buffer in advance, so that when read requests arrive, the data is already available in the cache, avoiding cache pollution from reactive replacement policies and improving read performance.

Inventive Principle:
Principle #10Preliminary action

4Ease of operation

If write requests are processed immediately in SSD, then write operations are simple, but number of NAND flash writes increases

Engineering Contradiction:
Improvewrite operation simplicityVSAvoidnumber of write requests to NAND flash
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent applies merging by combining multiple small write requests into larger write operations. The SSD controller buffers incoming write requests and merges them into larger write units before writing to NAND flash, reducing the total number of backend writes while maintaining fast write performance, thereby extending SSD endurance.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4357928B1Methods and system for efficient access to solid state drive
Publication Date: 2025.06.04 SAMSUNG ELECTRONICS CO LTD
  • EP4357928B1 patent drawingFigure 1
  • EP4357928B1 patent drawingFigure 2
  • EP4357928B1 patent drawingFigure 3

AI summary

Methods and memory devices are provided. A request is received from a host device at a memory device in a first state. In case that the request is a read request, first data is read from a cache of the memory device based on the read request, and the first data is output to the host device. The cache is loaded with data with the memory device in a second state. In case that the request is a write request, a block of the cache is modified to remove cache data, the cache data and corresponding data from the cache are written to a flash memory of the memory device, and second data is written to the block of the cache based on the received write request.