SSD Cache Tiering Using Internal Busy Information

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Solution Overview

Problem

NAND SSDs experience performance degradation due to background operations like defragmentation, which negatively impact overall system performance in disk caching and tiering configurations.

Innovation Solution

The implementation of a system that detects internal busy information of NAND SSDs, allowing an external processor to adjust the hierarchical data placement policy by skipping data inserts during busy periods and performing cache flushes and prefetching during idle conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If background operations (defragmentation, data scrubbing, wear leveling) are performed on NAND SSDs, then storage reliability and data management are improved, but system throughput and quality of service deteriorate

Engineering Contradiction:
Improvestorage reliabilityVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by proactively detecting background operations before they impact performance and preemptively adjusting caching policies. The external processor monitors internal information from the NAND SSD and anticipates busy periods, allowing the system to prepare cache flushes and data placement decisions in advance, thereby preventing performance degradation rather than reacting to it.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The caching policy dynamically adapts based on the operational state of the NAND SSD. The external processor adjusts cache behavior in real-time by monitoring internal information, switching between aggressive caching during idle periods and conservative caching during busy periods. This dynamic adjustment allows the system to optimize performance under varying conditions without fixed rigid policies.

Inventive Principle:
Principle #15Dynamics

2Speed

If data is continuously written to SSD cache, then read performance and hit rates are improved, but write operations during busy periods cause performance degradation

Engineering Contradiction:
Improveread performanceVSAvoidwrite operation efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The system performs preliminary actions by detecting background operations before they impact performance and preemptively adjusting caching policies. The external processor monitors internal information from the NAND SSD and anticipates busy periods, allowing the system to prepare cache flushes and data placement decisions in advance, thereby preventing performance degradation rather than reacting to it.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The caching policy dynamically adapts based on the operational state of the NAND SSD. The external processor adjusts cache behavior in real-time by monitoring internal information, switching between aggressive caching during idle periods and conservative caching during busy periods. This dynamic adjustment allows the system to optimize performance under varying conditions without fixed rigid policies.

Inventive Principle:
Principle #15Dynamics

3Productivity

If hierarchical data placement policy is aggressive during busy periods, then data availability is improved, but cache miss rates increase

Engineering Contradiction:
Improvedata availabilityVSAvoidcache hit rate
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The system implements feedback by continuously monitoring internal information from the NAND SSD and using this information to adjust caching policies. The external processor receives feedback about the SSD's operational state (busy/idle conditions) and modifies cache behavior accordingly, creating a closed-loop control system that optimizes performance based on real-time conditions rather than operating with fixed policies.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12253945B2Disk caching and/or tiering with device internal busy information
Publication Date: 2025.03.18 INTEL NDTM US LLC
  • US12253945B2 patent drawing
  • US12253945B2 patent drawing
  • US12253945B2 patent drawing

AI summary

Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.