SSD Memory Cell Verification for Over-Programming Detection
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Solution Overview
Problem
Existing solid-state drives (SSDs) face challenges in detecting over-programming of memory cells, leading to data errors and failures that disrupt data center services due to the lack of effective methods for handling over-programmed cells, particularly in high-capacity NAND flash devices used in hyper-scale data centers and AI data processing.
Innovation Solution
Implementing a double verification method for the lower and upper tails, or first and last bits of each state, to detect over-programming in SSDs, adjusting program operations with smaller pulse voltage steps, and retiring over-programmed blocks to prevent data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a program operation is performed to write data to multiple states of a memory cell, then data storage capacity is improved, but over-programming occurs causing data errors and reliability degradation
Solution Approach 1:
The patent performs preliminary verification of the upper tail bit before completing the program operation to a higher state. This preliminary check detects potential over-programming conditions before they cause data errors, allowing the system to prevent the harmful effect while maintaining the ability to store multiple states.
Solution Approach 2:
The patent implements a feedback mechanism where the verification result of the upper tail bit is used to control whether the program operation should be aborted. This feedback loop continuously monitors the programming process and takes corrective action when over-programming is detected, resolving the contradiction between storing more data and maintaining reliability.
2Speed
If verification is performed only for the lower tail bit, then programming speed is improved, but over-programming conditions go undetected causing data errors
Solution Approach 1:
The patent adds a partial verification action (checking the upper tail bit) to the existing lower tail bit verification. This excessive verification of specific critical bits provides the additional protection needed to detect over-programming without requiring complete verification of all bits, thus maintaining reasonable programming speed while improving reliability.
3Reliability
If the program pulse voltage step size is reduced to prevent over-programming, then data reliability is improved, but programming time increases
Solution Approach 1:
The patent performs preliminary verification of the upper tail bit during the programming process to detect over-programming conditions early. This allows the use of larger program pulse voltage step sizes without causing data errors, as the preliminary check provides safety net that compensates for the increased step size, thus maintaining both reliability and programming speed.
Data Source
AI summary
A method of detecting an over-programming of a memory cell during a write operation in a non-volatile memory media of a solid-state drive, and a solid-state drive with over-programming detection. When data is written to the states of the memory cell, a current last bit is routinely or selectively checked to detect an over-programming condition of the current state. An over-programming verification level may be used to check the current last bit and may be between zero and twenty-five millivolts lower than a regular programming verification level for a next first bit of the next state. When the over-programming condition is not detected, the program operation continues to write data to the next state. When the over-programming condition is detected, either the over-programmed current last bit is identified and the program operation is adjusted, or a memory block in which the over-programmed current last bit is located is retired.