SSD Collision Check Unit Offloading for Latency Reduction
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Solution Overview
Problem
Current solid state storage devices (SSDs) face inefficiencies in collision check operations, leading to increased processing latency and wear on memory cells due to the need for frequent read and write operations to the logical-to-physical (L2P) table for collision bit management.
Innovation Solution
Offloading collision check operations to a separate collision check unit implemented in hardware, allowing parallel processing with the controller firmware, eliminating the need for collision bits in the L2P table and reducing the frequency of memory accesses for collision checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If collision check operations are performed using the controller firmware accessing the L2P table, then the collision detection function is implemented, but processing latency increases and memory cell wear increases
Solution Approach 1:
The patent divides the collision check function from the main controller firmware into a separate dedicated collision check unit. This segmentation allows the collision detection operation to be performed independently from other controller tasks, enabling parallel processing and reducing the time the main controller spends on collision checks, thereby reducing processing latency while maintaining detection accuracy.
Solution Approach 2:
The patent introduces a dedicated collision check unit as an intermediary component between the host interface and the L2P table. This specialized unit is responsible solely for performing collision detection by checking the collision bit in L2P table entries, freeing the main controller firmware from this task and reducing overall processing latency while ensuring accurate collision detection.
2Reliability
If collision bits are managed in the L2P table through frequent read and write operations, then collision information is tracked, but memory cell wear increases
Solution Approach 1:
The patent extracts the collision check operation from the general controller firmware workflow and places it in a dedicated collision check unit. This extraction reduces the frequency with which the L2P table is accessed for collision bit management, as the dedicated unit can efficiently check collision status without requiring full L2P table read/write cycles, thereby reducing memory cell wear while maintaining accurate collision tracking.
3Device complexity
If the controller firmware processes all I/O requests sequentially, then resource management is simplified, but I/O request processing speed decreases
Solution Approach 1:
The patent segments the I/O request processing function into two independent parallel paths: the main controller firmware handles resource allocation and data transfer, while a separate collision check unit handles collision detection. This segmentation enables concurrent execution of these tasks, increasing I/O request processing speed without significantly increasing overall system complexity.
Solution Approach 2:
The patent creates a composite processing architecture where the controller firmware and collision check unit work together as integrated components. The firmware manages high-level resource allocation while the collision check unit handles specific collision detection tasks, combining their capabilities to achieve faster I/O processing while maintaining manageable complexity through clear division of labor.
Data Source
AI summary
Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.