SSD Command and Data Lane Separation for Concurrent Read Access
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Solution Overview
Problem
Conventional data storage access protocols fail to efficiently utilize the faster read speeds and concurrent read/write capabilities of solid-state storage devices, as younger read commands are delayed until older write commands are completed, leading to underutilization of communication channels and reduced IOPS performance.
Innovation Solution
Implementing a data storage access protocol that prioritizes and concurrently handles younger read commands alongside older write commands by using dedicated and dynamically configurable lanes in the physical interface, allowing simultaneous data transmission via separate command and data interfaces, thereby optimizing the utilization of communication channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data storage access protocols are used to handle write commands, then write operations are completed, but younger read commands are delayed until the write command finishes, reducing read throughput and channel utilization
Solution Approach 1:
The patent segments the communication interface into separate command and data lanes, allowing independent transmission of commands and data. This enables the storage device to receive newer read commands through command lanes while simultaneously transmitting data for older write commands through data lanes, eliminating the sequential dependency that caused read command delays.
Solution Approach 2:
The patent introduces a temporal dimension to command handling by allowing overlapping execution of write and read operations. By using separate command and data interfaces, the system transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing model where commands and data can be transmitted independently in time.
2Productivity
If solid-state drives are used with conventional protocols, then storage capacity is provided, but the ability to concurrently handle read and write commands is not utilized, reducing IOPS performance
Solution Approach 1:
The patent makes the communication interface multi-functional by separating it into dedicated command lanes and data lanes. The command lanes universally handle all command types (read, write, etc.) while data lanes handle data transmission, allowing the storage device to concurrently process multiple types of operations without protocol limitations.
Solution Approach 2:
The patent introduces dynamic command queuing and prioritization mechanisms that allow the storage device to adaptively handle incoming read and write commands. The system can dynamically allocate resources and prioritize operations based on current workload conditions, enabling efficient concurrent processing of multiple command types.
3Productivity
If a single communication interface is used for both commands and data, then interface simplicity is maintained, but channel utilization is reduced when concurrent read/write operations are needed
Solution Approach 1:
The patent segments the unified communication interface into separate command and data sub-interfaces. This segmentation allows independent optimization of command and data transmission, enabling full utilization of available bandwidth for both control and data operations simultaneously, thereby improving overall channel utilization.
Solution Approach 2:
The patent adds a functional dimension to the communication interface by separating command and data pathways. This dimensional separation transforms the interface from a single shared channel to a multi-channel structure, enabling parallel transmission of commands and data without interference and maximizing channel utilization.
Data Source
AI summary
A non-volatile storage system includes: a host and a storage device. The host includes a submission queue memory, a completion queue memory, and a read/write data memory, and the storage device includes: a controller configured to concurrently communicate with the read/write data memory and with at least one of the submission queue memory and the completion queue memory; and a memory device configured to communicate with the controller.