SSD Controller Buffer Memory Allocation for I/O Latency

The patent applies preliminary action by allocating buffer memory and DMA addresses in advance before the I/O operation is actually needed. The controller pre-allocates buffer memory regions and their corresponding DMA addresses during idle periods or in parallel with other operations, so that when data I/O is requested, the allocation is already complete or nearly complete, significantly reducing the latency associated with sequential allocation.

The patent implements continuity of useful action by maintaining buffer memory allocation and DMA address registration as ongoing processes rather than discrete sequential steps. The controller continuously manages buffer memory pools and DMA address spaces, allowing it to quickly grant allocations without interrupting the main I/O flow, thus keeping the system continuously productive without idle waiting periods.

The patent segments the I/O processing into multiple parallel paths: buffer memory allocation, DMA address registration, and actual data transfer occur as separate but coordinated operations rather than a single sequential process. This segmentation allows each component to operate independently and in parallel, improving overall I/O speed while maintaining manageable system complexity through clear separation of concerns.

The patent introduces dynamic parallel execution where the controller can simultaneously perform buffer allocation, DMA registration, and initiate data transfers based on real-time system conditions. The system dynamically adjusts the timing and ordering of these operations to maximize throughput, transforming the static sequential process into a flexible dynamic system that adapts to workload demands.