SSD Controller Compressing Host Data via Flash Translation Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The management of compressed data with variable lengths in nonvolatile memory systems, such as NAND-flash-type SSDs, poses challenges due to differences in data length between uncompressed and compressed data, leading to increased burden on data management and potential inefficiencies in storage and access.
Innovation Solution
A storage device and control method that compresses data received from a host into shorter lengths, generates address mappings to efficiently manage physical storage, and updates lookup tables to handle differences in data lengths, allowing for efficient data access and reduced storage requirements by using a flash translation layer to manage logical and physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data compression is performed on the host before writing to SSD, then storage efficiency is improved, but data management burden on the server side increases
Solution Approach 1:
The patent introduces a flash translation layer as an intermediary between the host and the NAND flash memory. This FTL performs data compression and manages address mappings, shielding the host from the complexity of variable-length compressed data management while maintaining storage efficiency benefits
Solution Approach 2:
The storage device autonomously performs data compression and manages its own address mappings through the flash translation layer, eliminating the need for the host to track compressed data lengths and manage storage details, thus reducing server-side management burden
2Volume of stationary object
If compressed data of variable lengths is stored in nonvolatile memory, then physical storage capacity is reduced, but address mapping complexity increases
Solution Approach 1:
The patent segments the logical address space into multiple regions and uses a multi-level caching structure with different types of address mapping tables. This segmentation allows efficient handling of variable-length compressed data by organizing mappings in manageable segments rather than requiring a single complex mapping structure
Solution Approach 2:
The patent introduces an additional dimension to address mapping by implementing a hierarchical cache structure with multiple levels and types of mapping tables. This multi-dimensional approach simplifies the mapping process by breaking down the complex one-to-one mapping into multiple layers of abstraction
3Quantity of substance
If data length differences between uncompressed and compressed data are managed, then storage efficiency improves, but access time increases
Solution Approach 1:
The patent performs preliminary actions by pre-computing and caching address mappings in multiple levels of translation caches. When data is written or read, the FTL has already prepared the necessary address translations, eliminating the need for complex real-time calculations and reducing access time
Solution Approach 2:
The patent changes the parameters of address mapping by implementing a hierarchical cache structure with different granularities and types of mapping tables. This allows the system to optimize for both storage efficiency and access speed by selecting appropriate mapping levels based on the specific access pattern
Data Source
AI summary
A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. Further, the controller is configured to generate an address mapping for the data, such that a first logical address range that starts at the starting logical address is mapped to a physical region of the nonvolatile storage having a size equal to the second data length, and a second logical address range that directly follows the first logical address range is not mapped to any physical region of the nonvolatile storage.