SSD Controller Debug Circuit for Failure Data Retrieval
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Solution Overview
Problem
In memory systems, particularly SSDs, debugging information is difficult to acquire when a CPU or bus failure occurs, as conventional methods require a dedicated debugger, and existing systems cannot retrieve data from DRAM, NAND memory, or registers without operational CPU and bus functionality.
Innovation Solution
A memory system with a controller that includes decoders, circuits, and a switching mechanism, allowing data access from DRAM, NAND memory, and SRAM using NVMe or PCIe commands, enabling data retrieval even in failure scenarios by transitioning to a debug mode that bypasses the normal CPU and bus pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a dedicated debugger is connected to the SSD to acquire debugging information, then debugging information can be acquired, but the debugging process becomes complicated and requires external equipment
Solution Approach 1:
The SSD controller performs self-debugging by including a debug circuit that can read data from internal memories (DRAM, NAND memory, SRAM) and registers without requiring external debugger equipment. The controller switches to a debug mode where the debug circuit directly accesses internal components, enabling the system to debug itself autonomously.
2Reliability
If the CPU and bus are operational, then normal data access and control functions work properly, but debugging information cannot be acquired when CPU or bus failure occurs
Solution Approach 1:
The debug circuit acts as an intermediary that can access internal memories and registers independently of the CPU and bus. When CPU or bus failure occurs, the debug circuit provides an alternative pathway to read debugging information directly from the failed system's internal components, bypassing the failed CPU and bus pathways.
Solution Approach 2:
The controller dynamically switches between normal operation mode and debug mode. In normal mode, the CPU and bus handle data access. In debug mode, the switching circuit redirects access paths to allow the debug circuit to read from internal memories and registers without involving the CPU or bus, enabling debugging even when they fail.
3Loss of information
If conventional debugging methods are used requiring dedicated equipment, then debugging information can be retrieved, but device complexity and operational difficulty increase
Solution Approach 1:
The debug circuit is merged into the SSD controller itself, combining the debugging functionality with the existing control architecture. This integration eliminates the need for separate external debugger equipment, as the controller contains all necessary components (debug circuit, switching circuit, decoders) to perform debugging operations internally.
Data Source
AI summary
According to one embodiment, a memory system includes a first memory and a controller. The controller includes first and second decoders, first and second circuits, a register, and a switching circuit. The first and second decoders decode first and second commands respectively, which include first and second addresses respectively. The first and second circuits access the first memory using the first and second addresses respectively. A value stored in the register is changeable by a host. The switching circuit switches between the first and second circuits to access the first memory according to the value in the register.