SSD Controller Latency Stabilization via Adaptive Delay
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Solution Overview
Problem
Solid-state drives (SSDs) using multi-level NAND flash devices face significant latency issues due to the need to erase blocks before rewriting, leading to inconsistent write command latencies, which can cause performance degradation, especially in enterprise applications where consistent latency is crucial.
Innovation Solution
The SSD controller measures the latency of each write command, tracks latency violations using counters, and adjusts the minimum duration for write command completion to maintain consistent latency within a predetermined tolerance, using an adaptive scheme that updates based on workload conditions and counter values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level NAND flash devices are used for persistent storage, then storage capacity is improved, but write command latency becomes inconsistent and large
Solution Approach 1:
The patent applies preliminary action by pre-erasing flash blocks before they are needed for writing data. The controller monitors write commands and proactively erases blocks that will be needed soon, so that when write operations occur, the blocks are already ready to receive data without requiring erase operations during the write process. This eliminates the need to wait for erase operations to complete before writing, thereby reducing write command latency while maintaining the high storage capacity of multi-level NAND flash devices.
2Adaptability or versatility
If blocks are erased before rewriting, then data can be rewritten to the same location, but write command latency increases significantly
Solution Approach 1:
The controller performs erase operations in advance before the actual write commands are issued. By monitoring write command patterns and predicting which blocks will be rewritten, the controller proactively erases those blocks beforehand. This ensures that when write commands arrive, the target blocks are already in the erased state and ready to accept data immediately, eliminating the need to wait for erase operations during write execution.
Solution Approach 2:
The patent implements skipping by allowing write operations to proceed without waiting for erase operations to complete. The controller decouples the write operation from the erase operation by performing erases in the background beforehand. When a write command is received, if the block is already erased (from preliminary action), the write operation can immediately proceed without being blocked by the erase process, thus rushing through the write operation without latency penalty.
3Speed
If write completion is transmitted immediately after write command, then response time is reduced, but observed latency varies outside tolerance
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual latency of write operations and comparing it against the minimum duration threshold. The controller measures the time between write command issuance and write completion, and uses this feedback information to dynamically adjust the minimum duration parameter. This closed-loop control ensures that the system maintains consistent observed latency within the specified tolerance range while still providing fast response times, as the minimum duration is optimized based on actual operational conditions rather than being a fixed conservative value.
Data Source
AI summary
Devices, systems and methods for maintaining consistent write latencies in non-volatile memory devices are described. An example method includes receiving, from a host device, a write command, computing an actual latency of the write command based on an arrival of the write command and a completion of the write command, incrementing, based on the actual latency, one or more of a plurality of counters, updating, based on the plurality of counters subsequent to the incrementing, a value of a minimum duration, and transmitting, at a time instance determined based on an updated value of the minimum duration, an indication of the completion of the write command to the host device, wherein the minimum duration represents a minimum latency between the arrival and the transmitting, and wherein transmitting at the time instance enables an observed latency to remain within a predetermined tolerance of an average value of the actual latency.