SSD Controller Parallel Address Translation CPUs
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Solution Overview
Problem
Conventional SSD controllers with a single flash translation layer (FTL) in a multi-channel parallel array structure are limited in processing multiple instructions simultaneously, restricting the performance of semiconductor memory devices and data access capabilities due to the inherent unit operation size mismatch between erase and write operations in flash memory.
Innovation Solution
A solid state drive (SSD) controller with multiple address translation central processing units (CPUs) and flash memory controllers that perform logical-physical address translations in parallel, including wear leveling and bad-block management, to handle multiple channels independently and optimize data access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single flash translation layer (FTL) is used in a multi-channel parallel array structure, then device complexity is reduced, but processing speed and productivity are limited due to inability to process multiple instructions simultaneously
Solution Approach 1:
The patent divides the single FTL into multiple FTLs, with each FTL dedicated to managing specific channels in the multi-channel parallel array structure. This segmentation enables parallel processing of instructions across different channels, significantly improving data processing speed and IOPS while maintaining manageable complexity through modular organization
Solution Approach 2:
The patent transitions from a single-channel sequential processing model to a multi-channel parallel processing model by adding the channel dimension. Multiple FTLs operate simultaneously on different channels, transforming the processing architecture from one-dimensional sequential execution to multi-dimensional parallel execution, thereby大幅提升 productivity
2Productivity
If multiple channels are provided in parallel array structure, then data access capability is improved, but instruction processing functionality is restricted due to single FTL limitation
Solution Approach 1:
The patent assigns dedicated FTLs to specific channels, allowing each channel to be independently managed and processed. This segmentation enables the instruction processing functionality to operate on multiple channels simultaneously without interference, thereby improving data access capability while maintaining ease of operation through dedicated channel management
Solution Approach 2:
Each FTL in the patent is designed to handle multiple functions including address translation, wear leveling, and bad block management for its assigned channels. This multi-functionality allows the system to maintain ease of operation while supporting multiple channels, as each FTL can independently manage its channel without requiring complex coordination
3Adaptability or versatility
If unit operation size mismatch between erase and write operations is addressed using FTL, then adaptability is improved, but processing speed is limited by sequential single FTL operation
Solution Approach 1:
The patent segments the address translation and control functions across multiple FTLs, each handling specific channels. This allows different channels to process different operations (erase or write) simultaneously with appropriate unit operation sizes, improving adaptability to various operation requirements while increasing processing speed through parallel execution
Solution Approach 2:
The patent implements dynamic channel assignment and FTL activation based on the specific operation requirements. When write operations need to be performed, the system can dynamically activate appropriate FTLs for those channels, while leaving other channels available for concurrent erase operations. This dynamic approach improves both adaptability to different operation sizes and overall processing speed through optimized resource utilization
Data Source
AI summary
A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.