SSD Controller Performance Estimation for Array Coordination

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Solution Overview

Problem

In NAND flash solid state drives (SSDs), the write performance can be reduced due to internal operations such as garbage collection, thermal throttling, and power restriction, leading to inefficiencies in data distribution across SSDs in a storage array, which can result in bottlenecks and increased power consumption.

Innovation Solution

A memory system that includes a controller capable of estimating the reduction in write performance due to internal operations and notifying the host or other SSDs, allowing for coordinated reduction in write performance across the SSD array, enabling efficient data distribution and power management by designating a sending-side SSD to notify and adjust the write performance of other SSDs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If garbage collection, thermal throttling, or power restriction operations are executed in an SSD, then reliability and thermal management are improved, but write performance is reduced

Engineering Contradiction:
ImprovereliabilityVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The sending-side SSD notifies the host or other SSDs about its reduced write performance through feedback mechanisms. This allows the system to respond adaptively by redistributing data or adjusting operations, thereby maintaining overall system reliability while managing the performance degradation caused by garbage collection, thermal throttling, or power restriction operations.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If write performance is reduced in one SSD, then power consumption is saved, but data distribution efficiency across the SSD array deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoiddata distribution efficiency
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system dynamically adjusts data distribution across the SSD array based on real-time performance status. When an SSD enters a reduced performance state, the host or controller redistributes data to other SSDs with available capacity, optimizing the balance between power consumption and data distribution efficiency in the entire array.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

By implementing feedback mechanisms where SSDs report their performance status, the system can dynamically reallocate data streams to maintain efficient data distribution across the array while allowing individual SSDs to reduce power consumption during their operational cycles.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If uncoordinated performance reduction occurs in SSDs, then individual power saving is achieved, but system-wide bottlenecks increase

Engineering Contradiction:
Improvepower savingVSAvoidsystem coordination complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Multiple SSDs are merged into a coordinated system where performance reduction in one SSD is communicated to others. This combining approach allows the system to treat performance variations as a unified challenge, distributing the impact across multiple devices rather than allowing uncoordinated individual optimizations that could create bottlenecks.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10592117B2Memory system and method for controlling nonvolatile memory
Publication Date: 2020.03.17 KIOXIA CORP
  • US10592117B2 patent drawing
  • US10592117B2 patent drawing
  • US10592117B2 patent drawing

AI summary

According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory, and an internal operation for managing the memory system. When starting the internal operation, the controller estimates a value related to an amount of reduction in performance of the write operation due to the start of the internal operation, based on content of the started internal operation, and notifies the host or one or more other semiconductor storage devices of the estimated value.