SSD Controller Power Circuit Testing via Command Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solid State Drive (SSD) power circuits are prone to failure due to unanticipated current spikes, as existing designs are based on maximum current specifications from NAND datasheets, which do not account for simultaneous spikes across multiple NAND dies, leading to potential damage from untested power conditions.
Innovation Solution
A storage device controller with embedded test programs that access a test matrix of command patterns to identify and test the power capabilities of shared power circuitry, specifically issuing command patterns that cause the greatest total current draw and potentially induce malfunctions, allowing for rigorous testing and qualification of power characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power circuits are designed based on maximum current specifications in NAND datasheets, then the design process is simple and follows standard specifications, but the circuits are prone to failure from unanticipated current spikes that exceed RMS current values
Solution Approach 1:
The patent applies preliminary action by implementing a power testing mechanism that proactively identifies current spike conditions before they cause circuit failure. The controller executes test programs that issue commands to NAND devices and monitor power consumption to detect damaging current spikes in advance, allowing designers to qualify power circuits against realistic workload conditions rather than relying solely on theoretical RMS current specifications.
2Measurement precision
If standard testing techniques are used to obtain power characteristics information, then some additional power data can be obtained, but damaging power conditions caused by simultaneous power spikes are rarely caught because host-generated workloads do not specifically exercise multiple NAND dies at once
Solution Approach 1:
The patent applies segmentation by dividing the power testing process into distinct command patterns that systematically exercise different combinations of NAND dies. The test program contains multiple command patterns that issue commands to individual dies, pairs of dies, and all dies simultaneously, allowing each segment of the power consumption profile to be measured and identified separately, including the identification of the command pattern that causes the greatest total current draw.
Solution Approach 2:
The patent applies dynamics by implementing an adaptive testing approach where the controller dynamically adjusts the testing based on observed power consumption. The system monitors power consumption during execution of different command patterns and identifies the specific pattern causing maximum current draw, allowing the test to focus on the most damaging conditions rather than using static, predetermined test sequences.
3Reliability
If comprehensive power testing with multiple command patterns is implemented, then damaging power conditions can be identified and reliability improved, but the testing process becomes more complex and requires embedded test programs and test matrices
Solution Approach 1:
The patent applies universality by designing a multi-functional controller that integrates both normal storage operations and power testing capabilities within a single device. The controller firmware contains embedded test programs that can execute alongside or instead of normal storage functions, allowing the same hardware to serve dual purposes: standard data storage operations and comprehensive power consumption testing, thereby reducing the need for separate dedicated testing equipment.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present invention extends to methods, systems, and computer program products for testing storage device power circuitry (113). A storage device controller (102) includes an embedded test program (104). The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns (107A,..., 107C) to test shared power circuitry (113) of storage device components (e.g., shared by an array of NAND flash memory devices (108A,..., 108C)). The test program identifies a command pattern (107) that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.