Controller Package Power Supply IC Integration for SSD Yield

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Solution Overview

Problem

Conventional SSDs with a SATA interface lack a power supply IC and passive elements, limiting power supply voltage for the controller and NAND flash memories, and complicating testing, which reduces yield.

Innovation Solution

Incorporating a power supply IC and passive elements as a module within the semiconductor storage device, allowing for multiple power supplies and enabling separate testing of controller and memory packages to improve yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a multi-chip package structure is used to stack NAND flash memories and controller, then integration is improved, but testing becomes difficult after sealing and total yield decreases

Engineering Contradiction:
ImproveintegrationVSAvoidtotal yield
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The device is divided into separate functional modules: a first module containing the controller and a second module containing the NAND flash memories. These modules are tested independently before being connected through wire bonds, allowing defect identification and replacement before final sealing, thereby maintaining high integration while enabling comprehensive testing to ensure total yield.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If no power supply IC is provided in conventional SSDs, then device complexity is reduced, but power supply flexibility is limited and lower voltage operation is not possible

Engineering Contradiction:
Improvedevice complexityVSAvoidpower supply flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

A power supply IC is introduced as an intermediary component in the first module, positioned between the external power source and the controller. This power supply IC converts the external power supply voltage to a lower operational voltage required by the controller, enabling flexible power supply options and lower voltage operation without significantly increasing overall device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If all components are sealed together in a single package, then manufacturing is simplified, but testing and quality guarantee become difficult

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidtesting difficulty
Core Design Contradiction:
Ease of manufactureVSDifficulty of detecting and measuring

Solution Approach 1:

Testing is performed on the controller and NAND flash memories separately before they are connected and sealed together. The controller module is tested for proper operation, and the NAND flash memory module is tested independently. Only after both modules pass their respective tests are they connected through wire bonds and sealed, ensuring high quality while maintaining manufacturing efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2720267B1Semiconductor storage device and method for producing the same
Publication Date: 2020.12.23 AMKOR TECH JAPAN INC
  • EP2720267B1 patent drawingFigure 1
  • EP2720267B1 patent drawingFigure 2
  • EP2720267B1 patent drawingFigure 3

AI summary

A semiconductor storage device (100) includes a controller package (110) having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages (120) each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.