SSD Controller Segmentation for Bus Load Reduction
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Solution Overview
Problem
Existing solid-state storage drives face challenges in achieving both high interface rates and high capacity specifications due to the increased load rate on input/output buses, which leads to decreased interface rates and increased data read/write delays.
Innovation Solution
The implementation of a solid-state storage drive that includes a controller, a selector, and N NAND flash memory chips, where the controller outputs gating signals to the selector to selectively route data through a portion of the NAND flash memory chips, thereby reducing the load on input/output buses and improving interface rates without compromising capacity specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of NAND flash memory chips connected to a same input/output bus increases to meet higher capacity specifications, then the storage capacity of the solid-state storage drive is improved, but the load rate of the input/output bus increases causing the interface rate to decrease and data read/write delay to increase
Solution Approach 1:
The patent divides the single input/output bus into multiple independent input/output buses (I/O bus 0, I/O bus 1, etc.), and segments the NAND flash memory chips into different channel groups. Each channel group is connected to a separate bus, allowing parallel data transmission and reducing the load on each individual bus. This segmentation enables the system to maintain high interface rates while supporting large storage capacities through multiple chips.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple channel groups that can operate simultaneously. Instead of increasing capacity along a single bus dimension, the system adds temporal and spatial parallelism through multiple channels, allowing data to be transmitted across multiple buses at the same time, thereby maintaining high interface rates while achieving high capacity.
2Quantity of substance
If the quantity of NAND flash memory chips connected to a same input/output bus increases to meet higher capacity specifications, then the storage capacity of the solid-state storage drive is improved, but the data read/write delay increases
Solution Approach 1:
By segmenting chips into channel groups connected to separate buses, the patent enables parallel read/write operations across multiple channels. This reduces the time required for data access by distributing the workload across multiple independent pathways, thereby decreasing data read/write delay while maintaining high storage capacity.
Solution Approach 2:
The patent implements continuous data transmission across multiple channel groups by allowing parallel operations on different buses simultaneously. This eliminates idle time and ensures continuous useful action, reducing overall data access delay while supporting large numbers of memory chips.
3Productivity
If the load rate of the input/output bus is controlled to improve the interface rate, then the interface rate of the solid-state storage drive is improved, but the capacity specifications are affected
Solution Approach 1:
The patent resolves this contradiction by segmenting the system into multiple channel groups, each with its own dedicated bus. This allows the load rate on each individual bus to remain controlled and manageable, maintaining high interface rates, while the aggregate storage capacity is expanded by adding more channel groups and chips across the segmented architecture.
Data Source
AI summary
A solid-state storage drive and a solid-state storage drive control method are provided. The solid-state storage drive includes a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1. The controller is configured to output a plurality of gating signals to the selector. The plurality of gating signals indicate M of the N NAND flash memory chips, where M is an integer greater than or equal to 1 and less than or equal to N. The selector is configured to select, based on the plurality of gating signals, the M NAND flash memory chips to perform data transmission. This improves an interface rate of the solid-state storage drive, so that performance requirements of a high interface rate and a high storage capacity of the solid-state storage drive can be satisfied.